(

)

æ

ö

+

=

´ ç

÷

ç

÷

è

ø

ON1

ON2

ON2

R

R

VIN _ UVLO

1.24 V

R

=

m

´

ON1

VIN _ HYS

15 A

R

UDG-11118

UVLO

+

TPS40322

VIN_OK

15 mA

TPS40322

www.ti.com

SLUSAF8

– JUNE 2011

Overvoltage and Undervoltage Fault Protection

The TPS40322 has output overvoltage protection and undervoltage protection capability. The comparators that

regulate the overvoltage and undervoltage conditions use the FBx pin as the output sensing point so the filtering

effect of the compensation network connected from COMPx to FBx has an effect on the speed of detection. As

the output voltage rises or falls below the nominal value, the error amplifier attempts to force FBx to match its

reference voltage. When the error amplifier is no longer able to do this, the FB pin begins to drift and trip the

CHARACTERISTICS table.

When an undervoltage fault is detected, the TPS40322 enters hiccup mode and resumes normal operation when

the fault is cleared.

When an overvoltage fault is detected, the TPS40322 turns off the high-side MOSFET and latches on the

low-side MOSFET to discharge the output current to the regulation level (within the power good window)

When operating in dual-channel mode, both channels have identical but independent protection schemes which

means one channel would not be affected when the other channel is in fault mode.

When operating in multi-phase mode, only the FB1 pin is detected for overvoltage and undervoltage fault.

Therefore both channels take action together during a fault.

Input Undervoltage Lockout (UVLO)

A dedicated UVLO pin allows the user to program the desired input turn-on threshold voltage. The diagram is

shown in Figure 22. The desired input turn-on threshold can be calculated using Equation 6. The input turn off

hysteresis can be calculated using Equation 7.

(6)

(7)

Figure 22. Input UVLO Diagram

Power Good

The TPS40322 provides an indication that output is good for each channel. This is an open-drain signal and pulls

low when any condition exists that would indicate that the output of the supply might be out of regulation. These

conditions include:

•

•

Soft-start is active

Thermal Shutdown

If the junction temperature of the device reaches the thermal shutdown limit of 150

°C, the PWMs and the

oscillators are turned off and HDRVs and LDRVs are driven low. When the junction cools to the required level

(130

°C typical), the PWM initiates soft start as during a normal power-up cycle.

Copyright

© 2011, Texas Instruments Incorporated

19