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AD6643 Datasheet(PDF) 32 Page - Analog Devices |
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AD6643 Datasheet(HTML) 32 Page - Analog Devices |
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32 / 36 page  AD6643 Rev. 0 | Page 32 of 36 Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Default Notes/ Comments 0x1D User Test Pattern 3 LSB (global) User Test Pattern 3[7:0] 0x00 0x1E User Test Pattern 3 MSB (global) User Test Pattern 3[15:8] 0x00 0x1F User Test Pattern 4 LSB (global) User Test Pattern 4[7:0] 0x00 0x20 User Test Pattern 4 MSB (global) User Test Pattern 4[15:8] 0x00 0x24 BIST signature LSB (local) BIST signature[7:0] 0x00 Read only 0x25 BIST signature MSB (local) BIST signature[15:8] 0x00 Read only Digital Feature Control Registers 0x3A Sync control (global) Open Open Open Open Open Open Clock divider sync enable 0 = off 1 = on Master sync enable 0 = off 1 = on 0x00 Control register to synchronize the clock divider 0x3C NSR control (local) Open Open Open Open NSR mode 000 = 22% BW mode 001 = 33% BW mode NSR enable 0 = off 1 = on 0x00 Noise shaping requantizer (NSR) controls 0x3E NSR tuning word (local) Open Open NSR tuning word See the Noise Shaping Requantizer (NSR) section Equations for the tuning word are dependent on the NSR mode 0x1C NSR frequency tuning word 0x59 SYNC pin control (local) Open Open Open Open Open Open SYNC pin sensitivity 0 = sync on high level 1 = sync on edge SYNC pin edge sensitivity 0 = sync on negative edge 1 = sync on positive edge 1 The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00. MEMORY MAP REGISTER DESCRIPTION For more information on functions controlled in Register 0x00 to Register 0x25, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, available at www.analog.com. Sync Control (Register 0x3A) Bits[7:3]—Reserved Bit 2—Clock Divider Next Sync Only If the master sync enable buffer bit (Address 0x3A, Bit0) and the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit 2 allows the clock divider to sync to the first sync pulse it receives and to ignore the rest. The clock divider sync enable bit (Address 0x3A, Bit 1) resets after it syncs. Bit 1—Clock Divider Sync Enable Bit 1 gates the sync pulse to the clock divider. The sync signal is enabled when Bit 1 is high and Bit 0 is high. This is continuous sync mode. Bit 0—Master Sync Buffer Enable Bit 0 must be set high to enable any of the sync functions. If the sync capability is not used this bit should remain low to conserve power. |
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