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AD6643 Datasheet(PDF) 26 Page - Analog Devices |
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AD6643 Datasheet(HTML) 26 Page - Analog Devices |
26 / 36 page ![]() AD6643 Rev. 0 | Page 26 of 36 CHANNEL/CHIP SYNCHRONIZATION The AD6643 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A. The SYNC input is internally synchronized to the sample clock. However, to ensure that there is no timing uncertainty between multiple parts, synchronize the SYNC input signal to the input clock signal. Drive the SYNC input using a single-ended CMOS type signal. Using Bit 1 in Register 0x59, the SYNC input can be set to either level or edge sensitive mode. If the SYNC input is set to edge sensitive mode, use Bit 0 of Register 0x59 to determine whether the rising or falling edge is used. |
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