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AD6643 Datasheet(PDF) 23 Page - Analog Devices

Part # AD6643
Description  Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6643 Datasheet(HTML) 23 Page - Analog Devices

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AD6643
Rev. 0 | Page 23 of 36
power-down, the output drivers are placed in a high impedance
state. Asserting the PDWN pin low returns the AD6643 to its
normal operating mode. Note that PDWN is referenced to the
digital output driver supply (DRVDD) and should not exceed
that supply voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering power-
down mode and then must be recharged when returning to normal
operation. As a result, wake-up time is related to the time spent
in power-down mode, and shorter power-down cycles result in
proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map Register
Description section and the AN-877 Application Note, Interfacing
to High Speed ADCs via SPI, available at www.analog.com for
additional details.
DIGITAL OUTPUTS
The AD6643 output drivers can be configured for either ANSI
LVDS or reduced drive LVDS using a 1.8 V DRVDD supply.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
Digital Output Enable Function (OEB)
The AD6643 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled using the OEB pin
or through the SPI interface. If the OEB pin is low, the output
data drivers are enabled. If the OEB pin is high, the output data
drivers are placed in a high impedance state. This OEB function
is not intended for rapid access to the data bus. Note that OEB
is referenced to the digital output driver supply (DRVDD) and
should not exceed that supply voltage.
When using the SPI interface, the data outputs of each channel
can be independently three-stated by using the output disable
bar bit (Bit 4) in Register 0x14. Because the output data is inter-
leaved, if only one of the two channels is disabled, the data from
the remaining channel is repeated in both the rising and falling
output clock cycles.
Timing
The AD6643 provides latched data with a pipeline delay of 10 input
sample clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
To reduce transients within the AD6643, minimize the length of
the output data lines and loads that are placed on them. These
transients can degrade converter dynamic performance.
The lowest typical conversion rate of the AD6643 is 40 MSPS. At
clock rates below 40 MSPS, dynamic performance can degrade.
Data Clock Output (DCO)
The AD6643 also provides data clock output (DCO) intended for
capturing the data in an external register. Figure 2 shows a
graphical timing diagram of the AD6643 output modes.
Table 11. Output Data Format
Input (V)
VIN+ − VIN−,
Input Span = 1.75 V p-p (V)
Offset Binary Output Mode
Twos Complement Mode (Default)
OR
VIN+ − VIN−
Less than −0.875
000 0000 0000
100 0000 0000
1
VIN+ − VIN−
−0.875
000 0000 0000
100 0000 0000
0
VIN+ − VIN−
0
100 0000 0000
000 0000 0000
0
VIN+ − VIN−
+ 0.875
111 1111 1111
011 1111 1111
0
VIN+ − VIN−
Greater than + 0.875
111 1111 1111
011 1111 1111
1


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