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AD6643 Datasheet(PDF) 22 Page - Analog Devices |
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AD6643 Datasheet(HTML) 22 Page - Analog Devices |
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22 / 36 page  AD6643 Rev. 0 | Page 22 of 36 0.1µF 0.1µF 0.1µF 0.1µF 100Ω PECL DRIVER 50kΩ 50kΩ CLK– CLK+ CLOCK INPUT CLOCK INPUT AD95xx ADC Figure 36. Differential LVDS Sample Clock (Up to 625 MHz) Input Clock Divider The AD6643 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. The duty cycle stabilizer (DCS) is enabled by default on power-up. The AD6643 clock divider can be synchronized using the external SYNC input. Bit 1 and Bit 2 of Register 0x3A allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written. A valid SYNC causes the clock divider to reset to its initial state. This synchro- nization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. Clock Duty Cycle Typical high speed ADCs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. Commonly, a ±5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD6643 contains a duty cycle stabilizer (DCS) that retimes the nonsampling (falling) edge, thereby providing an internal clock signal with a nominal 50% duty cycle. This allows the user to provide a wide range of clock input duty cycles without affecting the performance of the AD6643. Jitter on the rising edge of the input clock is of paramount concern and is not reduced by the duty cycle stabilizer. The duty cycle control loop does not function for clock rates of less than 40 MHz nominally. The loop has a time constant associated with it that must be considered when the clock rate can change dynamically. A wait time of 1.5 μs to 5 μs is required after a dynamic clock frequency increase or decrease before the DCS loop is relocked to the input signal. During the time period that the loop is not locked, the DCS loop is bypassed, and internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the DCS. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fIN) due to jitter (tJ) can be calculated by SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ] ) 10 / ( LF SNR − In the equation, the rms aperture jitter represents the root mean square of all jitter sources, which include the clock input, the analog input signal, and the ADC aperture jitter specification. IF undersampling applications are particularly sensitive to jitter, as shown in Figure 37. 80 75 70 65 60 55 50 1 10 100 1k INPUT FREQUENCY (MHz) 0.05ps 0.20ps 0.50ps 1.00ps 1.50ps MEASURED Figure 37. SNR vs. Input Frequency and Jitter In cases where aperture jitter may affect the dynamic range of the AD6643, treat the clock input as an analog signal. Separate power supplies for clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock at the last step. Refer to the AN-501 Application Note, Aperture Uncertainty and ADC System Performance, and the AN-756 Application Note, Sample Systems and the Effects of Clock Phase Noise and Jitter, for more information about jitter performance as it relates to ADCs (see www.analog.com). POWER DISSIPATION AND STANDBY MODE As shown in Figure 38, the power dissipated by the AD6643 is proportional to its sample rate. The data in Figure 38 was taken using the same operating conditions as those used for the Typical Performance Characteristics. 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.25 0.20 0.15 0.10 0.05 0 0 40 60 80 100 120 140 160 180 200 ENCODE FREQUENCY (MSPS) TOTAL POWER IAVDD IDRVDD Figure 38. AD6643 Power and Current vs. Sample Rate By asserting PDWN (either through the SPI port or by asserting the PDWN pin high), the AD6643 is placed in power-down mode. In this state, the ADC typically dissipates 10 mW. During |
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