AD6643 datasheet(14/36 Pages) AD

Part #	AD6643

Description	Dual IF Receiver 1.8 V supply voltages Internal ADC voltage reference

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AD6643

Rev. 0 | Page 14 of 36

Pin No.

Mnemonic

Type

Description

16

B D3+/D4+

Output

Channel B LVDS Output Data 3/Data 4—True.

17

B D5−/D6−

Output

Channel B LVDS Output Data 5/Data 6—Complement.

18

B D5+/D6+

Output

Channel B LVDS Output Data 5/Data 6—True.

20

B D7−/D8−

Ouput

Channel B LVDS Output Data 7/Data 8—Complement.

21

B D7+/D8+

Output

Channel B LVDS Output Data 7/Data 8—True.

22

B D9−/D10− (MSB)

Output

Channel B LVDS Output Data 9/Data 10—Complement.

23

B D9+/D10+ (MSB)

Output

Channel B LVDS Output Data 9/Data 10—True.

29

A 0/D0− (LSB)

Output

Channel B LVDS Output 0/Data 1—Complement. The first output bit from this

output is always a Logic 0.

30

A 0/D0+ (LSB)

Output

Channel B LVDS Output 0/Data 1—True. The first output bit from this output is

always a Logic 0.

31

A D1−/D2−

Output

Channel A LVDS Output Data 1/Data 0—Complement.

32

A D1+/D2+

Output

Channel A LVDS Output Data 1/Data 0—True.

33

A D3−/D4−

Output

Channel A LVDS Output Data 3/Data 2—Complement.

34

A D3+/D4+

Output

Channel A LVDS Output Data 3/Data 2—True.

35

A D5−/D6−

Output

Channel A LVDS Output Data 5/Data 4—Complement.

36

A D5+/D6+

Output

Channel A LVDS Output Data 5/Data 4—True.

38

A D7−/D8−

Output

Channel A LVDS Output Data 7/Data 6—Complement.

39

A D7+/D8+

Output

Channel A LVDS Output Data 7/Data 6—True.

40

A D9−/D10− (MSB)

Output

Channel A LVDS Output Data 9/Data 8—Complement.

41

A D9+/D10+ (MSB)

Output

Channel A LVDS Output Data 9/Data 8—True.

43

OR+

Output

Channel A/Channel B LVDS Overrange Output—True.

42

OR−

Output

Channel A/Channel B LVDS Overrange Output—Complement.

25

DCO+

Output

Channel A/Channel B LVDS Data Clock Output—True.

24

DCO−

Output

Channel A/Channel B LVDS Data Clock Output—Complement.

SPI Control

45

SCLK

Input

SPI Serial Clock (SCKL). The serial shift clock input, which is used to

synchronize serial interface reads and writes.

44

SDIO

Input/Output

SPI Serial Data Input/Output (SDIO). A dual purpose pin that typically serves as

an input or an output, depending on the instruction being sent and the

relative position in the timing frame.

46

CSB

Input

SPI Chip Select Bar (Active Low). An active low control that gates the read and

write cycles.

ADC Configuration

47

OEB

Input

Output Enable Input (Active Low).

48

PDWN

Input

Power-Down Input (Active High). The operation of this pin depends on the SPI

mode and can be configured as power-down or standby (see Table 14).

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