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AD6643 Datasheet(PDF) 12 Page - Analog Devices |
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AD6643 Datasheet(HTML) 12 Page - Analog Devices |
12 / 36 page ![]() AD6643 Rev. 0 | Page 12 of 36 Pin No. Mnemonic Type Description 27 D4+ Output Channel A/Channel B LVDS Output Data 4—True. 26 D4− Output Channel A/Channel B LVDS Output Data 4—Complement. 30 D5+ Output Channel A/Channel B LVDS Output Data 5—True. 29 D5− Output Channel A/Channel B LVDS Output Data 5—Complement. 32 D6+ Output Channel A/Channel B LVDS Output Data 6—True. 31 D6− Output Channel A/Channel B LVDS Output Data 6—Complement. 34 D7+ Output Channel A/Channel B LVDS Output Data 7—True. 33 D7− Output Channel A/Channel B LVDS Output Data 7—Complement. 36 D8+ Output Channel A/Channel B LVDS Output Data 8—True. 35 D8− Output Channel A/Channel B LVDS Output Data 8—Complement. 39 D9+ Output Channel A/Channel B LVDS Output Data 9—True. 38 D9− Output Channel A/Channel B LVDS Output Data 9—Complement. 41 D10+ (MSB) Output Channel A/Channel B LVDS Output Data 10—True. 40 D10− (MSB) Output Channel A/Channel B LVDS Output Data 10—Complement. 43 OR+ Output Channel A/Channel B LVDS Overrange—True. 42 OR− Output Channel A/Channel B LVDS Overrange—Complement. 25 DCO+ Output Channel A/Channel B LVDS Data Clock Output—True. 24 DCO− Output Channel A/Channel B LVDS Data Clock Output—Complement. SPI Control 45 SCLK Input SPI Serial Clock. The serial shift clock input, which is used to synchronize serial interface reads and writes. 44 SDIO Input/Output SPI Serial Data I/O. A dual purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. 46 CSB Input Chip Select Bar (Active Low). CSB gates the read and write cycles. Output Enable and Power-Down 47 OEB Input/Output Output Enable Input (Active Low). 48 PDWN Input/Output Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as power-down or standby (see Table 14). |
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