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SC16IS740 Datasheet(PDF) 14 Page - NXP Semiconductors

Part # SC16IS740
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS740 Datasheet(HTML) 14 Page - NXP Semiconductors

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SC16IS740_750_760
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 9 June 2011
14 of 63
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
[1]
Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the top-level reset signal
RESET, POR or Software Reset, that is, they hold their initialization values during reset.
[2]
This register is not supported in SC16IS740.
[3]
Only UART Software Reset bit is supported in this register.
Table 5 summarizes the state of registers after reset.
7.4.2 Power-on sequence
After power is applied, the device is reset by the internal POR. The host must wait at least
3
s before initializing a communication with the device.
An external reset pulse (see Figure 26) can also be used to reset the device after power is
applied.
Once the device is reset properly, the host processor can start to communicate with the
device. Internal registers can be accessed (read and write), however, at this time the
UART transmitter and receiver cannot be used until there is a stable clock at XTAL1 pin.
Normally, if an external clock such as a system clock or an external oscillator is used to
supply a clock to XTAL1 pin, the clock should be stable at this time. But if a crystal is used,
the host processor must wait until the crystal is generating a stable clock before accessing
the UART transmitter or receiver.
The crystal’s start-up time depends on the crystal being used, VCC ramp-up time and the
loading capacitor values. The start-up time can be as long as a few milliseconds.
Transmit FIFO level
reset to 0100 0000 (0x40)
Receive FIFO level
all bits cleared
I/O direction[2]
all bits cleared
I/O interrupt enable[2]
all bits cleared
I/O control[3]
all bits cleared
Extra Feature Register
all bits cleared
Table 5.
Output signals after reset
Signal
Reset state
TX
HIGH
RTS
HIGH
I/Os
inputs
IRQ
HIGH by external pull-up
Table 4.
Register reset[1]
Register
Reset state


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