SC16IS740_11 datasheet(51/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

51 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

Table 40.

SC16IS760 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD =2.5 V  0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V  0.3 V, Tamb = 40 Cto +95 C and refer to VIL and VIH with

an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.

Symbol

Parameter

Conditions

VDD =2.5 V

VDD =3.3 V

Unit

Min

Max

Min

Max

tTR

CS HIGH to SO 3-state delay time

CL = 100 pF

-

100

-

100

ns

tCSS

CS to SCLK setup time

100

-

100

-

ns

tCSH

CS to SCLK hold time

5

-

5

-

ns

tDO

SCLK fall to SO valid delay time

CL = 100 pF

-

25

-

20

ns

tDS

SI to SCLK setup time

10

-

10

-

ns

tDH

SI to SCLK hold time

10

-

10

-

ns

tCP

SCLK period

tCL + tCH

83

-

67

-

ns

tCH

SCLK HIGH time

30

-

25

-

ns

tCL

SCLK LOW time

30

-

25

-

ns

tCSW

CS HIGH pulse width

200

-

200

-

ns

td9

SPI output data valid time

200

-

200

-

ns

td10

SPI modem output data valid time

200

-

200

-

ns

td11

SPI transmit interrupt clear time

200

-

200

-

ns

td12

SPI modem input interrupt clear time

200

-

200

-

ns

td13

SPI interrupt clear time

200

-

200

-

ns

td14

SPI receive interrupt clear time

200

-

200

-

ns

tw(rst)

reset pulse width

3

-

3

-

s

Fig 35. Detailed SPI-bus timing

tCSH

tCSS

tCL

tCH

tCSH

tDO

tTR

tDS

tDH

SO

SI

SCLK

CS

002aab066

tCSW

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