SC16IS740_11 datasheet(50/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

50 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

[1]

Applies to external clock, crystal oscillator max. 24 MHz.

[2]

[3]

100 ppm is recommended.

Table 38.

fXTAL dynamic characteristics

VDD =2.5 V  0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V  0.3 V, Tamb = 40 Cto +95 C

Symbol

Parameter

Conditions

VDD =2.5 V

VDD =3.3 V

Unit

Min

Max

Min

Max

tw1

clock pulse duration

10

-

6

-

ns

tw2

clock pulse duration

10

-

6

-

ns

fXTAL

frequency on pin XTAL

[1][2]

-48[3]

-80

MHz

f

XTAL

1

t

w3

-------

=

Fig 34. External clock timing

EXTERNAL

CLOCK

002aaa112

tw3

tw2

tw1

Table 39.

SC16IS740/750 SPI-bus timing specifications

All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;

VDD =2.5 V  0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V  0.3 V, Tamb = 40 Cto +95 C; and refer to VIL and VIH with

an input voltage of VSS to VDD. All output load = 25 pF, unless otherwise specified.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tTR

CS HIGH to SO 3-state delay time

CL = 100 pF

-

100

ns

tCSS

CS to SCLK setup time

100

-

ns

tCSH

CS to SCLK hold time

20

-

ns

tDO

SCLK fall to SO valid delay time

CL = 100 pF

-

100

ns

tDS

SI to SCLK setup time

100

-

ns

tDH

SI to SCLK hold time

20

-

ns

tCP

SCLK period

tCL + tCH

250

-

ns

tCH

SCLK HIGH time

100

-

ns

tCL

SCLK LOW time

100

-

ns

tCSW

CS HIGH pulse width

200

-

ns

td9

SPI output data valid time

200

-

ns

td10

SPI modem output data valid time

200

-

ns

td11

SPI transmit interrupt clear time

200

-

ns

td12

SPI modem input interrupt clear time

200

-

ns

td13

SPI interrupt clear time

200

-

ns

td14

SPI receive interrupt clear time

200

-

ns

tw(rst)

reset pulse width

3

-

s

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