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SC16IS740 Datasheet(PDF) 47 Page - NXP Semiconductors

Part # SC16IS740
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS740 Datasheet(HTML) 47 Page - NXP Semiconductors

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SC16IS740_750_760
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 9 June 2011
47 of 63
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
14. Dynamic characteristics
[1]
A detailed description of the I2C-bus specification, with applications, is given in user manual UM10204: “I2C-bus specification and user
manual”. This may be found at www.nxp.com/documents/user_manual/UM10204.pdf.
[2]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
[3]
Only applicable to the SC16IS750 and SC16IS760.
[4]
2 XTAL1 clocks or 3
s, whichever is less.
Table 37.
I2C-bus timing specifications[1]
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD =2.5 V 0.2 V, Tamb = 40 Cto+85 C; or VDD =3.3 V 0.3 V, Tamb = 40 Cto +95 C; and refer to VIL and VIH with
an input voltage of VSS to VDD. All output load = 25 pF, except SDA output load = 400 pF.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
[2]
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.7
-
0.6
-
s
tHD;DAT
data hold time
0
-
0
-
ns
tVD;ACK
data valid acknowledge time
-
0.6
-
0.6
s
tVD;DAT
data valid time
SCL LOW to
data out valid
-0.6
-
0.6
ns
tSU;DAT
data set-up time
250
-
150
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tf
fall time of both SDA and SCL signals
-
300
-
300
ns
tr
rise time of both SDA and SCL signals
-
1000
-
300
ns
tSP
pulse width of spikes that must be
suppressed by the input filter
-50
-
50
ns
td1
I2C-bus GPIO output valid time
[3]
0.5
-
0.5
-
s
td2
I2C-bus modem input interrupt valid time
0.2
-
0.2
-
s
td3
I2C-bus modem input interrupt clear time
0.2
-
0.2
-
s
td4
I2C input pin interrupt valid time
0.2
-
0.2
-
s
td5
I2C input pin interrupt clear time
0.2
-
0.2
-
s
td6
I2C-bus receive interrupt valid time
0.2
-
0.2
-
s
td7
I2C-bus receive interrupt clear time
0.2
-
0.2
-
s
td8
I2C-bus transmit interrupt clear time
1.0
-
0.5
-
s
td15
SCL delay time after reset
[4]
3-
3
-
s
tw(rst)
reset pulse width
3
-
3
-
s


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