SC16IS740_11 datasheet(39/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

39 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

An address on the network is seven bits long, appearing as the most significant bits of the

address byte. The last bit is a direction (R/W) bit. A ‘0’ indicates that the master is

transmitting (write) and a ‘1’ indicates that the master requests data (read). A complete

data transfer, comprised of an address byte indicating a ‘write’ and two data bytes is

shown in Figure 21.

When an address is sent, each device in the system compares the first seven bits after

the START with its own address. If there is a match, the device will consider itself

addressed by the master, and will send an acknowledge. The device could also determine

if in this transaction it is assigned the role of a slave receiver or slave transmitter,

depending on the R/W bit.

Each node of the I2C-bus network has a unique seven-bit address. The address of a

microcontroller is of course fully programmable, while peripheral devices usually have

fixed and programmable address portions.

When the master is communicating with one device only, data transfers follow the format

of Figure 21, where the R/W bit could indicate either direction. After completing the

transfer and issuing a STOP condition, if a master would like to address some other

device on the network, it could start another transaction by issuing a new START.

Another way for a master to communicate with several different devices would be by using

a ‘repeated START’. After the last byte of the transaction was transferred, including its

acknowledge (or negative acknowledge), the master issues another START, followed by

address byte and data — without effecting a STOP. The master may communicate with a

number of different devices, combining ‘reads’ and ‘writes’. After the last transfer takes

place, the master issues a STOP and releases the bus. Possible data formats are

demonstrated in Figure 22. Note that the repeated START allows for both change of a

slave and a change of direction, without releasing the bus. We shall see later on that the

change of direction feature can come in handy even when dealing with a single device.

In a single master system, the repeated START mechanism may be more efficient than

terminating each transfer with a STOP and starting again. In a multimaster environment,

the determination of which format is more efficient could be more complicated, as when a

master is using repeated STARTs it occupies the bus for a long time and thus preventing

other devices from initiating transfers.

Fig 21. A complete data transfer

S

P

SDA

SCL

0 to 6

78

ACK

002aab046

START

condition

STOP

condition

address

R/W

0 to 6

78

data

ACK

0 to 6

78

data

ACK

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