SC16IS740_11 datasheet(38/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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38 / 63 page

SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

38 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

A slave receiver must generate an acknowledge after the reception of each byte, and a

master must generate one after the reception of each byte clocked out of the slave

transmitter.

There are two exceptions to the ‘acknowledge after every byte’ rule. The first occurs when

a master is a receiver: it must signal an end of data to the transmitter by not signalling an

acknowledge on the last byte that has been clocked out of the slave. The acknowledge

related clock, generated by the master should still take place, but the SDA line will not be

pulled down. In order to indicate that this is an active and intentional lack of

acknowledgement, we shall term this special condition as a ‘negative acknowledge’.

The second exception is that a slave will send a negative acknowledge when it can no

longer accept additional data bytes. This occurs after an attempted transfer that cannot be

accepted.

10.2 Addressing and transfer formats

Each device on the bus has its own unique address. Before any data is transmitted on the

bus, the master transmits on the bus the address of the slave to be accessed for this

transaction. A well-behaved slave with a matching address, if it exists on the network,

should of course acknowledge the master's addressing. The addressing is done by the

first byte transmitted by the master after the START condition.

Fig 19. Data transfer on the I2C-bus

S

P

SDA

SCL

MSB

0

1

6

7

8

0

1

2 to 7

8

ACK

002aab012

START

condition

STOP

condition

acknowledgement signal

from receiver

byte complete,

interrupt within receiver

clock line held LOW

while interrupt is serviced

Fig 20. Acknowledge on the I2C-bus

S

01

6

7

8

002aab013

data output

by transmitter

data output

by receiver

SCL from master

START

condition

transmitter stays off of the bus

during the acknowledge clock

acknowledgement signal

from receiver

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