SC16IS740_11 datasheet(36/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

Download	63 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

Logo

36 / 63 page

SC16IS740_750_760

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7 — 9 June 2011

36 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

9.2 RS-485 RTS output inversion

EFCR bit 5 reverses the polarity of the RTS pin if the UART is in auto RS-485 RTS mode.

When the transmitter has data to be sent it will deasserts the RTS pin (logic 1), and when

the last bit of the data has been sent out the transmitter asserts the RTS pin (logic 0).

9.3 Auto RS-485

EFCR bit 0 is used to enable the RS-485 mode (multidrop or 9-bit mode). In this mode of

operation, a ‘master’ station transmits an address character followed by data characters

for the addressed ‘slave’ stations. The slave stations examine the received data and

interrupt the controller if the received character is an address character (parity bit = 1).

To use the auto RS-485 mode the software would have to disable the hardware and

software flow control functions.

9.3.1 Normal multidrop mode

The 9-bit Mode in EFCR (bit 0) is enabled, but not Special Character Detect (EFR bit 5).

The receiver is set to Force Parity 0 (LCR[5:3] = 111) in order to detect address bytes.

With the receiver initially disabled, it ignores all the data bytes (parity bit = 0) until an

address byte is received (parity bit = 1). This address byte will cause the UART to set the

parity error. The UART will generate a line status interrupt (IER bit 2 must be set to ‘1’ at

this time), and at the same time puts this address byte in the RX FIFO. After the controller

examines the byte it must make a decision whether or not to enable the receiver; it should

enable the receiver if the address byte addresses its ID address, and must not enable the

receiver if the address byte does not address its ID address.

If the controller enables the receiver, the receiver will receive the subsequent data until

being disabled by the controller after the controller has received a complete message

from the ‘master’ station. If the controller does not disable the receiver after receiving a

message from the ‘master’ station, the receiver will generate a parity error upon receiving

another address byte. The controller then determines if the address byte addresses its ID

address, if it is not, the controller then can disable the receiver. If the address byte

addresses the ‘slave’ ID address, the controller take no further action, the receiver will

receive the subsequent data.

9.3.2 Auto address detection

If Special Character Detect is enabled (EFR[5] is set and the XOFF2 register contains the

address byte) the receiver will try to detect an address byte that matches the programmed

character in the XOFF2 register. If the received byte is a data byte or an address byte that

does not match the programmed character in the XOFF2 register, the receiver will discard

these data. Upon receiving an address byte that matches the Xoff2 character, the receiver

will be automatically enabled if not already enabled, and the address character is pushed

into the RX FIFO along with the parity bit (in place of the parity error bit). The receiver also

generates a line status interrupt (IER[2] must be set to ‘1’ at this time). The receiver will

then receive the subsequent data from the ‘master’ station until being disabled by the

controller after having received a message from the ‘master’ station.

If another address byte is received and this address byte does not match Xoff2 character,

the receiver will be automatically disabled and the address byte is ignored. If the address

byte matches Xoff2 character, the receiver will put this byte in the RX FIFO along with the

parity bit in the parity error bit (LSR bit 2).

Similar Part No. - SC16IS740_11

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	SC16IS740IPW	308Kb / 62P	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 05-16 November 2006
NXP Semiconductors	SC16IS740IPW	321Kb / 62P	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 06-13 May 2008

More results

Similar Description - SC16IS740_11

Manufacturer	Part #	Datasheet	Description
NXP Semiconductors	SC16IS740	321Kb / 62P	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 06-13 May 2008
	SC16IS741A	505Kb / 55P	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 1??8 March 2013
	SC16IS740	308Kb / 62P	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 05-16 November 2006
	SC16IS752	303Kb / 59P	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 07-19 May 2008
	SC16IS752IBS	482Kb / 60P	Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support Rev. 9-22 March 2012
	SC16C652	575Kb / 41P	Dual UART with 32 bytes of transmit and receive FIFOs Rev. 04-20 June 2003
Diodes Incorporated	PI7C9X760	3Mb / 53P	I2C-bus/SPI to UART Bridge Controller w/ 64 bytes of TX/RX FIFOs Rev 6 - 2 April 2019
NXP Semiconductors	SC16C2550	603Kb / 46P	Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder Rev. 03-19 June 2003
NXP Semiconductors	SC16C2550	603Kb / 46P	Dual UART with 16 bytes of transmit and receive FIFOs and infrared (IrDA) encoder/decoder Rev. 03-19 June 2003
Exar Corporation	ST16C2550	443Kb / 34P	DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFOS

More results

SC16IS740 Datasheet(PDF) 36 Page - NXP Semiconductors

SC16IS740 Datasheet(HTML) 36 Page - NXP Semiconductors

Similar Part No. - SC16IS740_11

Similar Description - SC16IS740_11

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL