SC16IS740_11 datasheet(35/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

35 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.21 Extra Features Control Register (EFCR)

[1]

For SC16IS760 only.

9.

RS-485 features

9.1 Auto RS-485 RTS control

Normally the RTS pin is controlled by MCR bit 1, or if hardware flow control is enabled, the

logic state of the RTS pin is controlled by the hardware flow control circuitry. EFCR

register bit 4 will take the precedence over the other two modes; once this bit is set, the

transmitter will control the state of the RTS pin. The transmitter automatically asserts the

RTS pin (logic 0) once the host writes data to the transmit FIFO, and deasserts RTS pin

(logic 1) once the last bit of the data has been transmitted.

To use the auto RS-485 RTS mode the software would have to disable the hardware flow

control function.

Table 31.

Extra Features Control Register bits description

Bit

Symbol

Description

7

IRDA MODE

IrDA mode

0 = IrDA SIR, 3



16 pulse ratio, data rate up to 115.2 kbit/s

1 = IrDA SIR, 1



4 pulse ratio, data rate up to 1.152 Mbit/s

[1]

6-

reserved

5

RTSINVER

invert RTS signal in RS-485 mode

0: RTS = 0 during transmission and RTS = 1 during reception

1: RTS = 1 during transmission and RTS = 0 during reception

4

RTSCON

enable the transmitter to control the RTS pin

0 = transmitter does not control RTS pin

1 = transmitter controls RTS pin

3-

reserved

2

TXDISABLE

Disable transmitter. UART does not send serial data out on the

transmit pin, but the transmit FIFO will continue to receive data from

host until full. Any data in the TSR will be sent out before the

transmitter goes into disable state.

0: transmitter is enabled

1: transmitter is disabled

1

RXDISABLE

Disable receiver. UART will stop receiving data immediately once this

bit set to a 1, and any data in the TSR will be sent to the receive FIFO.

User is advised not to set this bit during receiving.

0: receiver is enabled

1: receiver is disabled

0

9-BIT MODE

Enable 9-bit or Multidrop mode (RS-485).

0: normal RS-232 mode

1: enables RS-485 mode

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