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SC16IS740 Datasheet(PDF) 34 Page - NXP Semiconductors |
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SC16IS740 Datasheet(HTML) 34 Page - NXP Semiconductors |
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34 / 63 page  SC16IS740_750_760 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 9 June 2011 34 of 63 NXP Semiconductors SC16IS740/750/760 Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.20 I/O Control register (IOControl) This register is only available on the SC16IS750 and SC16IS760. Remark: As I/O pins, the direction, state, and interrupt of GPIO4 to GPIO7 are controlled by the following registers: IODir, IOState, IOIntEna, and IOControl. The state of CD, RI, DSR pins will not be reflected in MSR[7:5] or MSR[3:1], and any change of state on these three pins will not trigger a modem status interrupt (even if enabled via IER[3]), and the state of the DTR pin cannot be controlled by MCR[0]. As modem CD, RI, DSR pins, the status at the input of these three pins can be read from MSR[7:5] and MSR[3:1], and the state of DTR pin can be controlled by MCR[0]. Also, if modem status interrupt bit is enabled, IER[3], a change of state of RI, CD, DSR pins will trigger a modem interrupt. Bit[7:4] of the IODir, IOState, and IOIntEna registers will not have any effect on these three pins. Table 30. IOControl register bits description Bit Symbol Description 7:4 - reserved for future use 3 SRESET software reset A write to bit will reset the device. Once the device is reset this bit is automatically set to ‘0’ 2 - reserved for future use 1 GPIO[7:4] or modem pins This bit programs GPIO[7:4] as I/O pins or modem RI, CD, DTR, DSR pins. 0 = GPIO[7:4] behave as I/O pins 1 = GPIO[7:4] behave as RI, CD, DTR, DSR 0 IOLATCH enable/disable inputs latching 0 = input values are not latched. A change in any input generates an interrupt. A read of the input register clears the interrupt. If the input goes back to its initial logic state before the input register is read, then the interrupt is cleared. 1 = input values are latched. A change in the input generates an interrupt and the input logic value is loaded in the bit of the corresponding input state register (IOState). A read of the IOState register clears the interrupt. If the input pin goes back to its initial logic state before the interrupt register is read, then the interrupt is not cleared and the corresponding bit of the IOState register keeps the logic value that initiates the interrupt. |
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Similar Description - SC16IS740_11 |
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