SC16IS740_11 datasheet(33/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

33 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.16 Receiver FIFO Level register (RXLVL)

This register is a read-only register, it reports the fill level of the receive FIFO. That is, the

number of characters in the RX FIFO.

8.17 Programmable I/O pins Direction register (IODir)

This register is only available on the SC16IS750 and SC16IS760. This register is used to

program the I/O pins direction. Bit 0 to bit 7 controls GPIO0 to GPIO7.

Remark: If there is a pending input (GPIO) interrupt and IODir is written, this pending

interrupt will be cleared, that is, the interrupt signal will be negated.

8.18 Programmable I/O pins State Register (IOState)

This register is only available on the SC16IS750 and SC16IS760. When ‘read’, this

register returns the actual state of all I/O pins. When ‘write’, each register bit will be

transferred to the corresponding IO pin programmed as output.

8.19 I/O Interrupt Enable Register (IOIntEna)

This register is only available on the SC16IS750 and SC16IS760. This register enables

the interrupt due to a change in the I/O configured as inputs. If GPIO[7:4] are programmed

as modem pins, their interrupt generation must be enabled via IER register bit 3. In this

case bit 7 to bit 4 of IOIntEna will have no effect on GPIO[7:4].

Table 26.

Receiver FIFO Level register bits description

Bit

Symbol

Description

7

-

not used; set to zeros

6:0

RXLVL[6:0]

number of characters stored in RX FIFO, from 0 (0x00) to 64 (0x40)

Table 27.

IODir register bits description

Bit

Symbol

Description

7:0

IODir

set GPIO pins [7:0] to input or output

0 = input

1 = output

Table 28.

IOState register bits description

Bit

Symbol

Description

7:0

IOState

Write this register:

set the logic level on the output pins

0 = set output pin to zero

1 = set output pin to one

Read this register:

return states of all pins

Table 29.

IOIntEna register bits description

Bit

Symbol

Description

7:0

IOIntEna

input interrupt enable

0 = a change in the input pin will not generate an interrupt

1 = a change in the input will generate an interrupt

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