SC16IS740_11 datasheet(32/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

32 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.13 Transmission Control Register (TCR)

This 8-bit register is used to store the RX FIFO threshold levels to stop/start transmission

during hardware/software flow control. Table 23 shows Transmission Control Register bit

settings.

TCR trigger levels are available from 0 to 60 characters with a granularity of four.

Remark: TCR can only be written to when EFR[4] = 1 and MCR[2] = 1. The programmer

must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware

check to make sure this condition is met. Also, the TCR must be programmed with this

condition before auto RTS or software flow control is enabled to avoid spurious operation

of the device.

8.14 Trigger Level Register (TLR)

This 8-bit register is used to store the transmit and received FIFO trigger levels used for

interrupt generation. Trigger levels from 4 to 60 can be programmed with a granularity

of 4. Table 24 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[2] = 1. If TLR[3:0] or

TLR[7:4] are logical 0, the selectable trigger levels via the FIFO Control Register (FCR)

are used for the transmit and receive FIFO trigger levels. Trigger levels from 4 characters

to 60 characters are available with a granularity of four. The TLR should be programmed

for N



4, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the trigger

level setting defined in FCR. If TLR has non-zero trigger level value, the trigger level

defined in FCR is discarded. This applies to both transmit FIFO and receive FIFO trigger

level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

that is, ‘00’.

8.15 Transmitter FIFO Level register (TXLVL)

This register is a read-only register, it reports the number of spaces available in the

transmit FIFO.

Table 23.

Transmission Control Register bits description

Bit

Symbol

Description

7:4

TCR[7:4]

RX FIFO trigger level to resume

3:0

TCR[3:0]

RX FIFO trigger level to halt transmission

Table 24.

Trigger Level Register bits description

Bit

Symbol

Description

7:4

TLR[7:4]

RX FIFO trigger levels (4 to 60), number of characters available.

3:0

TLR[3:0]

TX FIFO trigger levels (4 to 60), number of spaces available.

Table 25.

Transmitter FIFO Level register bits description

Bit

Symbol

Description

7

-

not used; set to zeros

6:0

TXLVL[6:0]

number of spaces available in TX FIFO, from 0 (0x00) to 64 (0x40)

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