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SC16IS740 Datasheet(PDF) 31 Page - NXP Semiconductors |
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SC16IS740 Datasheet(HTML) 31 Page - NXP Semiconductors |
31 / 63 page ![]() SC16IS740_750_760 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 9 June 2011 31 of 63 NXP Semiconductors SC16IS740/750/760 Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 8.11 Enhanced Features Register (EFR) This 8-bit register enables or disables the enhanced features of the UART. Table 22 shows the enhanced feature register bit settings. 8.12 Division registers (DLL, DLH) These are two 8-bit registers which store the 16-bit divisor for generation of the baud clock in the baud rate generator. DLH stores the most significant part of the divisor. DLL stores the least significant part of the divisor. Remark: DLL and DLH can only be written to before Sleep mode is enabled, that is, before IER[4] is set. Table 22. Enhanced Features Register bits description Bit Symbol Description 7 EFR[7] CTS flow control enable logic 0 = CTS flow control is disabled (normal default condition) logic 1 = CTS flow control is enabled. Transmission will stop when a HIGH signal is detected on the CTS pin. 6 EFR[6] RTS flow control enable. logic 0 = RTS flow control is disabled (normal default condition) logic 1 = RTS flow control is enabled. The RTS pin goes HIGH when the receiver FIFO halt trigger level TCR[3:0] is reached, and goes LOW when the receiver FIFO resume transmission trigger level TCR[7:4] is reached. 5 EFR[5] Special character detect logic 0 = Special character detect disabled (normal default condition) logic 1 = Special character detect enabled. Received data is compared with Xoff2 data. If a match occurs, the received data is transferred to FIFO and IIR[4] is set to a logical 1 to indicate a special character has been detected. 4 EFR[4] Enhanced functions enable bit logic 0 = disables enhanced functions and writing to IER[7:4], FCR[5:4], MCR[7:5]. logic 1 = enables the enhanced function IER[7:4], FCR[5:4], and MCR[7:5] so that they can be modified. 3:0 EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 “Software flow control options (EFR[3:0])”. |
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