SC16IS740_11 datasheet(28/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

28 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.7 Modem Status Register (MSR)

This 8-bit register provides information about the current state of the control lines from the

modem, data set, or peripheral device to the host. It also indicates when a control input

from the modem changes state. Table 18 shows Modem Status Register bit settings.

[1]

Only available on SC16IS750/SC16IS760.

Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.

8.8 Scratch Pad Register (SPR)

This 8-bit register is used as a temporary data storage register. User’s program can

write to or read from this register without any effect on the operation of the device.

Table 18.

Modem Status Register bits description

Bit

Symbol

Description

7MSR[7]

CD[1] (active HIGH, logical 1). If GPIO6 is selected as CD modem pin

through IOControl register bit 1, the state of CD pin can be read from this

bit. This bit is the complement of the CD input. Reading IOState bit 6 does

not reflect the true state of CD pin.

6MSR[6]

RI[1] (active HIGH, logical 1). If GPIO7 is selected as RI modem pin through

IOControl register bit 1, the state of RI pin can be read from this bit. This bit

is the complement of the RI input. Reading IOState bit 6 does not reflect the

true state of RI pin.

5

MSR[5]

DSR[1] (active HIGH, logical 1). If GPIO4 is selected as DSR modem pin

through IOControl register bit 1, the state of DSR pin can be read from this

bit. This bit is the complement of the DSR input. Reading IOState bit 4 does

not reflect the true state of DSR pin.

4

MSR[4]

CTS (active HIGH, logical 1). This bit is the complement of the CTS input.

3MSR[3]

CD[1]. Indicates that CD input has changed state. Cleared on a read.

2MSR[2]

RI[1]. Indicates that RI input has changed state from LOW to HIGH.

Cleared on a read.

1MSR[1]

DSR[1]. Indicates that DSR input has changed state. Cleared on a read.

0MSR[0]

CTS. Indicates that CTS input has changed state. Cleared on a read.

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