SC16IS740_11 datasheet(27/63 Pages) NXP

Part #	SC16IS740

Description	Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs

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Manufacturer	NXP [NXP Semiconductors]

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SC16IS740_750_760

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Product data sheet

Rev. 7 — 9 June 2011

27 of 63

NXP Semiconductors

SC16IS740/750/760

Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

8.6 Modem Control Register (MCR)

The MCR controls the interface with the mode, data set, or peripheral device that is

emulating the modem. Table 17 shows the Modem Control Register bit settings.

[1]

MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.

[2]

Only available on SC16IS750/SC16IS760.

Table 17.

Modem Control Register bits description

Bit

Symbol

Description

7

MCR[7][1]

clock divisor

logic 0 = divide-by-1 clock input

logic 1 = divide-by-4 clock input

6

MCR[6][1]

IrDA mode enable

logic 0 = normal UART mode

logic 1 = IrDA mode

5

MCR[5][1]

Xon Any

logic 0 = disable Xon Any function

logic 1 = enable Xon Any function

4

MCR[4]

enable loopback

logic 0 = normal operating mode

logic 1 = enable local Loopback mode (internal). In this mode the

MCR[1:0] signals are looped back into MSR[4:5] and the TX output is

looped back to the RX input internally.

3

MCR[3]

reserved

2

MCR[2]

TCR and TLR enable

logic 0 = disable the TCR and TLR register.

logic 1 = enable the TCR and TLR register.

1

MCR[1]

RTS

logic 0 = force RTS output to inactive (HIGH)

logic 1 = force RTS output to active (LOW). In Loopback mode,

controls MSR[4]. If Auto RTS is enabled, the RTS output is controlled

by hardware flow control.

0

MCR[0]

DTR[2]. If GPIO5 is selected as DTR modem pin through IOControl

register bit 1, the state of DTR pin can be controlled as below. Writing to

IOState bit 5 will not have any effect on this pin.

logic 0 = Force DTR output to inactive (HIGH)

logic 1 = Force DTR output to active (LOW)

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