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SC16IS740 Datasheet(PDF) 20 Page - NXP Semiconductors

Part # SC16IS740
Description  Single UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SC16IS740 Datasheet(HTML) 20 Page - NXP Semiconductors

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SC16IS740_750_760
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 7 — 9 June 2011
20 of 63
NXP Semiconductors
SC16IS740/750/760
Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.
Register descriptions
The programming combinations for register selection are shown in Table 9.
[1]
MCR[7] can only be modified when EFR[4] is set.
[2]
Accessible only when ERF[4] = 1 and MCR[2] = 1, that is, EFR[4] and MCR[2] are read/write enables.
[3]
Available only on SC16IS750/SC16IS760.
[4]
Accessible only when LCR[7] is logic 1.
[5]
Accessible only when LCR is set to 1011 1111b (0xBF).
Fig 16. Crystal oscillator circuit reference
002aab402
1.8432 MHz
C1
22 pF
C2
33 pF
XTAL1
XTAL2
Table 9.
Register map - read/write properties
Register name Read mode
Write mode
RHR/THR
Receive Holding Register (RHR)
Transmit Holding Register (THR)
IER
Interrupt Enable Register (IER)
Interrupt Enable Register
IIR/FCR
Interrupt Identification Register (IIR)
FIFO Control Register (FCR)
LCR
Line Control Register (LCR)
Line Control Register
MCR
Modem Control Register (MCR)[1]
Modem Control Register[1]
LSR
Line Status Register (LSR)
n/a
MSR
Modem Status Register (MSR)
n/a
SPR
Scratchpad Register (SPR)
Scratchpad Register
TCR
Transmission Control Register (TCR)[2]
Transmission Control Register[2]
TLR
Trigger Level Register (TLR)[2]
Trigger Level Register[2]
TXLVL
Transmit FIFO Level Register
n/a
RXLVL
Receive FIFO Level Register
n/a
IODir[3]
I/O pin Direction Register
I/O pin Direction Register
IOState[3]
I/O pin States Register
n/a
IOIntEna[3]
I/O Interrupt Enable Register
I/O Interrupt Enable Register
IOControl[3]
I/O pins Control Register
I/O pins Control Register
EFCR
Extra Features Register
Extra Features Register
DLL
divisor latch LSB (DLL)[4]
divisor latch LSB[4]
DLH
divisor latch MSB (DLH)[4]
divisor latch MSB[4]
EFR
Enhanced Feature Register (EFR)[5]
Enhanced Feature Register[5]
XON1
Xon1 word[5]
Xon1 word[5]
XON2
Xon2 word[5]
Xon2 word[5]
XOFF1
Xoff1 word[5]
Xoff1 word[5]
XOFF2
Xoff2 word[5]
Xoff2 word[5]


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