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SC16IS740 Datasheet(PDF) 17 Page - NXP Semiconductors |
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SC16IS740 Datasheet(HTML) 17 Page - NXP Semiconductors |
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17 / 63 page  SC16IS740_750_760 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 7 — 9 June 2011 17 of 63 NXP Semiconductors SC16IS740/750/760 Single UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR 7.6 Sleep mode Sleep mode is an enhanced feature of the SC16IS740/750/760 UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • The serial data input line, RX, is idle (see Section 7.7 “Break and time-out conditions”). • The TX FIFO and TX shift register are empty. • There are no interrupts pending except THR. Remark: Sleep mode will not be entered if there is data in the RX FIFO. In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using these clocks, the power consumption is greatly reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem input pins, or if data is written to the TX FIFO. Wake-up by serial data on RX input pin is supported in UART mode but not in IrDA mode in Rev. C and Rev. D of the device. Refer to application note AN10964, “How to wake up SC16IS/740/750/760 in IrDA mode” for a software procedure to wake up the device by receiving data in the IrDA mode. Wake-up by serial data on RX input pin is supported in both UART mode and IrDA mode in Rev. E of the device. The device will not wake up by GPIO pin transition, but GPIO pin input state can be read, and GPIO interrupt is working normally during Sleep mode. Remark: Writing to the divisor latches, DLL and DLH, to set the baud clock, must not be done during Sleep mode. Therefore, it is advisable to disable Sleep mode using IER[4] before writing to DLL or DLH. 7.7 Break and time-out conditions When the UART receives a number of characters and these data are not enough to set off the receive interrupt (because they do not reach the receive trigger level), the UART will generate a time-out interrupt instead, 4 character times after the last character is received. The time-out counter will be reset at the center of each stop bit received or each time the receive FIFO is read. A break condition is detected when the RX pin is pulled LOW for a duration longer than the time it takes to send a complete character plus Start, Stop and Parity bits. A break condition can be sent by setting LCR[6]. When this happens the TX pin will be pulled LOW until LSR[6] is cleared by the software. |
Similar Part No. - SC16IS740_11 |
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Similar Description - SC16IS740_11 |
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