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ICE3PCS03G Datasheet(PDF) 11 Page - Infineon Technologies AG |
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ICE3PCS03G Datasheet(HTML) 11 Page - Infineon Technologies AG |
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11 / 20 page  CCM-PFC ICE3PCS03G Functional Description Version 2.0 11 5 May 2010 Figure 9 Average Current Control in CCM The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 3 (ICOMP). The PWM cycles starts with the Gate turn off for a duration of TOFFMIN (600ns typ.) and the ramp is kept discharged. The ramp is allowed to rise after the TOFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and the averaged current waveform. This results in the proportional relationship between the average current and the off duty cycle DOFF. Figure 10 shows the timing diagrams of the TOFFMIN and the gate waveforms. Figure 10 Ramp and PWM waveforms 3.7 PWM Logic The PWM logic block prioritizes the control input signal and generates the final logic signal to turn on the driver stage. The speed of the logic gates in this block, together with the width of the reset pulse TOFFMIN, are designed to meet a maximum duty cycle DMAX of 95% at the GATE output under 65kHz of operation. In case of high input currents which results in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal TOFFMIN resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 11. Figure 11 PWM LOGIC 3.8 System Protection The IC provides numerous protection features in order to ensure the PFC system in safe operation. 3.8.1 Input Voltage Brownout Protection(BOP) Brownout occurs when the input voltage VIN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the VCCUVLO level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. ICE3PCS03G provides a new BOP feature whereby it senses directly the input voltage for Input Brown-Out condition via an external resistor/capacitor/diode network shown in Figure 12. This network provides a filtered value of VIN which turns the IC on when the voltage at pin 5 (BOP) is more than 1.25V. The IC enters into the fault mode when BOP goes below 1.0V. The hysteresis prevents the system to oscillate between normal and fault mode. Note also that the peak of VIN needs to be at least 20% of the rated VOUT in order to overcome OLP and powerup system. Ramp Profile Ave(Iin) at ICOMP Gate Drive t t PWM Cycle Ramp Released Toff_min 600 ns Clock VC,ref (1) Vramp GATE (1)Vc,ref is a function of VICOMP R S Q Q Current limit Latch R S Q Q PWM on Latch High = turn on Gate Toff_min 600ns Peak current limit Current loop PWM on signal |
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