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FAN7930C Datasheet(PDF) 17 Page - Fairchild Semiconductor |
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FAN7930C Datasheet(HTML) 17 Page - Fairchild Semiconductor |
17 / 22 page ![]() © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7930C • Rev. 1.0.0 17 PCB Layout Guide PFC block normally handles high switching current and the voltage low energy signal path can be affected by the high energy path. Cautious PCB layout is mandatory for stable operation. 1. The gate drive path should be as short as possible. The closed-loop that runs from the gate driver, MOSFET gate, and MOSFET source to ground of PFC controller should be as close as possible. This is also crossing point between power ground and signal ground. Power ground path from the bridge diode to the output bulk capacitor should be short and wide. The sharing position between power ground and signal ground should be only at one position to avoid ground loop noise. Signal path of PFC controller should be short and wide for external components to contact. 2. PFC output voltage sensing resistor is normally high to reduce current consumption. This path can be affected by external noise. To reduce noise potential at the INV pin, a shorter path for output sensing is recommended. If a shorter path is not possible, place some dividing resistors between PFC output and the INV pin — closer to the INV pin is better. Relative high voltage close to the INV pin can be helpful. 3. ZCD path is recommended close to auxiliary winding from boost inductor and to the ZCD pin. If that is difficult, place a small capacitor (below 50pF) to reduce noise. 4. The switching current sense path should not share with another path to avoid interference. Some additional components may be needed to reduce the noise level applied to the CS pin. 5. A stabilizing capacitor for VCC is recommended as close as possible to the VCC and ground pins. If it is difficult, place the SMD capacitor as close to the corresponding pins as possible. Figure 44. Recommended PCB Layout |
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