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FAN7930C Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FAN7930C Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 22 page  © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAN7930C • Rev. 1.0.0 11 Applications Information 1. Startup: Normally, supply voltage (VCC) of a PFC block is fed from the additional power supply, which can be called standby power. Without this standby power, auxiliary winding for zero current detection can be used as a supply source. Once the supply voltage of the PFC block exceeds 12V, internal operation is enabled until the voltage drops to 8.5V. If VCC exceeds VZ, 20mA current is sinking from VCC. Figure 22. Startup Circuit 2. INV Block: Scaled-down voltage from the output is the input for the INV pin. Many functions are embedded based on the INV pin: transconductance amplifier, output OVP comparator, disable comparator, and output UVLO comparator. For the output voltage control, a transconductance amplifier is used instead of the conventional voltage amplifier. The transconductance amplifier (voltage- controlled current source) aids the implementation of the OVP and disable functions. The output current of the amplifier changes according to the voltage difference of the inverting and non-inverting input of the amplifier. To cancel down the line input voltage effect on power factor correction, the effective control response of the PFC block should be slower than the line frequency and this conflicts with the transient response of controller. Two- pole one-zero type compensation may be used to meet both requirements. The OVP comparator shuts down the output drive block when the voltage of the INV pin is higher than 2.675V and there is 0.175V hysteresis. The disable comparator disables operation when the voltage of the inverting input is lower than 0.35V and there is 100mV hysteresis. An external small-signal MOSFET can be used to disable the IC, as shown in Figure 23. The IC operating current decreases to reduce power consumption if the IC is disabled. Error! Reference source not found. is the timing chart of the internal circuit near the INV pin when rated PFC output voltage is 390VDC and VCC supply voltage is 15V. Figure 23. Circuit Around INV Pin Figure 24. Timing Chart for INV Block 3. RDY Output: When the INV voltage is higher than 2.24V, RDY output is triggered HIGH and lasts until the INV voltage is lower than 2.051V. When input AC voltage is quite high, for example 240VAC, PFC output voltage is always higher than RDY threshold, regardless of boost converter operation. In this case, the INV voltage is already higher than 2.24V before PFC VCC touches VSTART; however, RDY output is not triggered to HIGH until VCC touches VSTART. After boost converter operation stops, RDY is not pulled LOW because the INV voltage is higher than the RDY threshold. When VCC of the PFC drops below 5V, RDY is pulled LOW even though PFC output voltage is higher than threshold. The RDY pin output is open drain, so needs an external pull- up resistor to supply the proper power source. The RDY pin output remains floating until VCC is higher than 2V. |
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