AN-6961

APPLICATION NOTE

© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.2 • 4/8/09

5

10V

2.1V

1.75V

Gate

Inhibit time

t

t

t

Figure 14.

Maximum On-Time Operation

The on-time of the power MOSFET is varied with the output

power and the AC input voltage. While the AC input voltage

decreases,

the

on-time

increases

accordingly.

The

resistor connected between MOT and GND pin.

)

µs

(

24

25

)

k

(

•

Ω

=

max

on,

t

(4)

The range of the maximum on-time is designed to be within

10~50μs; 25μs is recommended.

loop failure. Once the protection is triggered, the PWM

output is turned off.

Peak Current Limiting

The switch current is sensed across a resistor and supplied

to an input terminal of a comparator. A voltage higher than

the 0.82V threshold voltage on the CS pin immediately

terminates the current switching cycle, activating cycle-by-

cycle current limiting.

Leading-Edge Blanking (LEB)

A turn-on spike inevitably occurs at the CS pin when the

power MOSFET is switched on. At the beginning of each

switching pulse, the current-limit comparator is disabled for

around 350ns to avoid premature termination. The gate drive

output cannot be switched off during the blanking period.

Under-Voltage Lockout (UVLO)

The turn-on and turn-off threshold voltages are fixed

internally at 12V and 9.5V, respectively. This hysteresis

behavior guarantees a one-shot start-up, as long as a

proper start-up resistor and hold-up capacitor are used.

Output Driver

With a low on resistance and a high current driving

capability, the output driver can drive an external capacitive

load larger than 3000pF. Cross conduction currents are

avoided to minimize heat dissipation, improving efficiency

and reliability. This output driver is internally clamped by a

17V Zener diode.

Lab Note

Before rework or solder/desolder on the power supply,

discharge the primary capacitors by external bleeding

resistor

. Otherwise, the PWM IC may be destroyed by

external high voltage during solder/desolder.

Design Guideline

PFC Inductor Design

As shown in Figure 15, considering one AC line voltage

peak of the AC line voltage. To avoid audible noise, the

frequency. The appropriate inductance can be calculated by

happen in AC maximum or minimum input voltage,

depending on the output voltage. Therefore, calculate both

the maximum and the minimum input voltages, then choose

the lower inductance value.

(

)

min

.

s

o

o

pk

o

2

pk

f

V

P

4

V

V

V

•

•

•

−

•

•

=

η

b

L

(5)

where:

η is conversion efficiency,

0.00E+00

1.00E+04

2.00E+04

3.00E+04

4.00E+04

5.00E+04

6.00E+04

7.00E+04

0

10

20

304050607080

Time(S/5000)

Switching Frequency

Line input voltage[Vin(t)*200]

Figure 15.

Frequency vs. Input Voltage

η

•

•

•

=

min

.

rms

o

V

2

P

4

L,pk

i

(6)

With the internal THD optimization circuit, the real peak

inductor current is smaller than calculated. Usually, the real

peak current is around 95% of calculated value.