AN-6961

APPLICATION NOTE

© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

Rev. 1.0.2 • 4/8/09

4

Figure 10 shows the measured input current on the

example circuit board.

Ch2: Before THD Optimization (1A/div);

Ref1: After THD Optimization (1A/div)

Figure 10.

Calculated Waveforms of the Input Current

(Before and After THD Optimization Circuit is Added)

Figure 11 shows the measured THD performance on the

example circuit board.

2

3

4

5

6

7

8

9

10

90

110

220

240

264

Vac(V)

THD Optimization

Fixed On-Time

Figure 11.

Measured THD Result at Full Load Condition

(Fixed On-time Technique vs. THD Optimization)

Over- / Under-Voltage Protection (OVP/UVP)

Over / under-voltage protection is built-in to provide

protection by detecting and examining the voltage on INV

conditions, the internal OVP protection circuit is triggered to

disable the PWM output. Over-voltage conditions are

usually caused by an open-loop feedback. A debounce time

around 35μs is added to prevent false triggering. If the

PWM output is turned off.

1

2

Figure 12. Block Diagram of the Over / Under- Voltage

Protection

Zero-Current Detection

Figure 13 shows the block diagram of the zero-current

detection. The zero inductor current detection is performed

by sensing the information on an auxiliary winding of the

PFC inductor. As shown in Figure 14, when Q turns off, the

stored energy of the inductor starts to release to the output.

The voltage on the ZCD starts to decrease when the energy

in the inductor dries out. Once the ZCD voltage is lower

than the threshold voltage (1.75V typical), the PWM output

is high again and initiates a new switching cycle. The output

rectifier is always turned off with zero current, so the

converter works in boundary mode conditions and the

power MOSFET is switched on with low voltage to minimize

the switching losses.

Once the ZCD voltage is lower than the disable threshold

voltage (around 0.25V) for a duration of about 800µs, the

PWM output is disabled.

To prevent high switching frequency during light load

conditions, an inhibit timer function is built in to limit the

maximum switching frequency.

33K~68K

Ω) connected from auxiliary winding to the ZCD

pin is recommended to improve noise immunity on the ZCD

pin.

Figure 13.

Block Diagram of the Zero-Current

Detection