IXYS reserves the right to change limits, test conditions, and dimensions.

IXFH36N55Q2

Fig. 11. Capacitance

100

1000

10000

0

5

10

15

20

25

30

35

40

Ciss

Coss

Crss

f = 1MHz

Fig. 10. Gate Charge

0

1

2

3

4

5

6

7

8

9

10

0

10

2030

4050

6070

8090 100 110

Fig. 7. Input Adm ittance

0

5

10

15

20

25

30

35

40

45

50

3

3.5

4

4.5

5

5.5

6

6.5

25ºC

-40ºC

Fig. 8. Transconductance

0

5

10

15

20

25

30

35

40

45

50

0

5

10

15

20

25

30

35

40

45

50

55

25ºC

125ºC

Fig. 9. Source Current vs.

Source-To-Drain Voltage

0

10

20

30

40

50

60

70

80

90

100

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

Fig. 12. Forw ard-Bias

Safe Operating Area

1

10

100

1000

10

100

1000

100µs

1ms

DC

10ms

25µs