K6R4008C1D

CMOS SRAM

PRELIMINARY

Rev. 2.0

- 3 -

July 2004

512K x 8 Bit High-Speed CMOS Static RAM

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 10ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 20mA(Max.)

(CMOS) : 5mA(Max.)

Operating K6R4008C1D-10 : 65mA(Max.)

• Single 5.0V

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Standard Pin Configuration

K6R4008C1D-J : 36-SOJ-400

K6R4008C1D-K : 36-SOJ-400(Lead-Free)

K6R4008C1D-T : 44-TSOP2-400BF

K6R4008C1D-U : 44-TSOP2-400BF(Lead-Free)

• Operating in Commercial and Industrial Temperature range.

The K6R4008C1D is a 4,194,304-bit high-speed Static Random

Access Memory organized as 524,288 words by 8 bits. The

K6R4008C1D uses 8 common input and output lines and has an

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG

′s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The K6R4008C1D is packaged

in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.

Clk Gen.

CS

WE

OE

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

1024 Rows

512 x 8 Columns

I/O Circuit