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K6R4008C1D Datasheet(PDF) 7 Page - Samsung semiconductor |
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K6R4008C1D Datasheet(HTML) 7 Page - Samsung semiconductor |
7 / 10 page ![]() K6R4008C1D CMOS SRAM PRELIMINARY Rev. 2.0 - 7 - July 2004 Address Data Out Previous Valid Data Valid Data TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH) tAA tRC tOH NOTES(WRITE CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. WRITE CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol K6R4008C1D-10 Unit Min Max Write Cycle Time tWC 10 - ns Chip Select to End of Write tCW 7- ns Address Set-up Time tAS 0- ns Address Valid to End of Write tAW 7- ns Write Pulse Width(OE High) tWP 7- ns Write Pulse Width(OE Low) tWP1 10 - ns Write Recovery Time tWR 0- ns Write to Output High-Z tWHZ 05 ns Data to Write Time Overlap tDW 5- ns Data Hold from Write Time tDH 0- ns End of Write to Output Low-Z tOW 3- ns Valid Data High-Z tRC CS Address OE Data out tHZ(3,4,5) tAA tCO tOE tOLZ tLZ(4,5) tOHZ tPU tPD 50% 50% VCC Current ICC ISB tDH TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH) |
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