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CY2DP1510 Datasheet(PDF) 6 Page - Cypress Semiconductor

Part # CY2DP1510
Description  1:10 LVPECL Fanout Buffer with Selectable Clock Input
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY2DP1510 Datasheet(HTML) 6 Page - Cypress Semiconductor

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CY2DP1510
Document Number: 001-55566 Rev. *G
Page 6 of 13
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Condition
Min
Typ
Max
Unit
FIN
Input frequency
DC
1.5
GHz
FOUT
Output frequency
FOUT = FIN
DC
1.5
GHz
VPP
LVPECL differential output voltage peak
to peak, single ended. Terminated with
50
Ω to V
DD – 2.0
[6]
Fout = DC to 150 MHz
600
mV
Fout = >150 MHz to 1.5 GHz
400
mV
tPD
[7]
Propagation delay input pair to output
pair
Input rise/fall time < 1.5 ns
(20% to 80%)
––
600
ps
tODC
[8]
Output duty cycle
50% duty cycle at input
Frequency range up to 1 GHz
48–52
%
tSK1
[9]
Output-to-output skew
Any output to any output, with
same load conditions at DUT
––
40
ps
tSK1 D
[9]
Device-to-device output skew
Any output to any output
between two or more devices.
Devices must have the same
input and have the same output
load.
––
150
ps
PNADD
Additive RMS phase noise
156.25-MHz input
Rise/fall time < 150 ps (20% to 80%)
VID > 400 mV
Offset = 1 kHz
–120
dBc/Hz
Offset = 10 kHz
–130
dBc/Hz
Offset = 100 kHz
–140
dBc/Hz
Offset = 1 MHz
–150
dBc/Hz
Offset = 10 MHz
–154
dBc/Hz
Offset = 20 MHz
–155
dBc/Hz
tJIT
[10]
Additive RMS phase jitter (Random)
156.25 MHz, 12 kHz to 20 MHz
offset; input rise/fall time <
150 ps (20% to 80%), VID >
400 mV
––
0.11
ps
tR,tF
[11]
Output rise/fall time
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
––
300
ps
Notes
6. Refer to Figure 3 on page 7.
7. Refer to Figure 4 on page 7.
8. Refer to Figure 5 on page 7.
9. Refer to Figure 6 on page 8.
10. Refer to Figure 7 on page 8.
11. Refer to Figure 8 on page 8.
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