CY2CP1504

Document Number: 001-56313 Rev. *F

Page 12 of 13

Document History Page

Document Title: CY2CP1504 1:4 LVCMOS to LVPECL Fanout Buffer with Selectable Clock Input

Document Number: 001-56313

Revision

ECN

Orig. of

Change

Submission

Date

Description of Change

**

2782891

CXQ

10/09/09

New Datasheet

*A

2838916

CXQ

05/01/2010

Changed status from “ADVANCE” to “PRELIMINARY”.

Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page

mA to 61 mA.

= 140 k

Ω.

page 4.

mV for DC - 150 MHz and min = 400 mV for 150 MHz to 250 MHz.

Changed letter case and some names of all the timing parameters in the AC

Electrical Specs table on page 5 to be consistent with EROS.

Lowered all additive phase noise mask specs by 3 dB in the AC Electrical

Specs table on page 5.

that input rise/fall time must be less than 1.5 ns (20% to 80%).

Changed letter case and some names of all the timing parameters in Figures

2, 3, 4, 5 and 7, to be consistent with EROS.

*B

3011766

CXQ

08/20/2010

Changed from 0.25 ps to 0.15 ps maximum additive jitter in “Features” on page

Removed reference to data distribution from “Functional Description”.

Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to

-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical

Specs table.

Updated package diagram.

Added Acronyms and Ordering Code Definition.

*C

3017258

CXQ

08/27/2010

Corrected Output Rise/Fall time diagram.

*D

3100234

CXQ

11/18/2010

Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec

JESD78B IC Latchup Test”

swing, 50% input duty cycle measured at Vdd/2”.

Changed phase jitter condition to “156.25 MHz sinewave, 12 kHz to 20 MHz

*E

3137726

CXQ

01/13/2011

Removed “Preliminary” status heading.

Removed resistors from IN0/IN1 in Logic Block Diagram.

*F

3182321

CXQ

02/25/11

Post to external web.

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