CY2CP1504

1:4 LVCMOS to LVPECL Fanout Buffer

with Selectable Clock Input

Cypress Semiconductor Corporation

•

198 Champion Court

•

San Jose

•

408-943-2600

Document Number: 001-56313 Rev. *F

Revised February 25, 2011

Features

semiconductor (LVCMOS) inputs to distribute to four

low-voltage positive emitter-coupled logic (LVPECL) output

pairs

(12-kHz to 20-MHz offset)

[1]

Functional Description

The

CY2CP1504

is

an

ultra-low

noise,

low-skew,

low-propagation delay 1:4 LVCMOS to LVPECL fanout buffer

targeted to meet the requirements of high-speed clock

distribution applications. The CY2CP1504 can select between

two separate LVCMOS input clocks using the IN_SEL pin. The

synchronous clock enable function ensures glitch-free output

transitions during enable and disable periods. The device has a

fully differential internal architecture that is optimized to achieve

low additive jitter and low skew at operating frequencies of up to

250 MHz.

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.

Logic Block Diagram

CLK_EN

Q0

Q0#

Q1

Q1#

Q2

Q2#

Q3

Q3#

IN0

IN1

100k

IN_SEL

100k

VDD

D

Q

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