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AT24C32D Datasheet(PDF) 7 Page - ATMEL Corporation |
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AT24C32D Datasheet(HTML) 7 Page - ATMEL Corporation |
7 / 26 page ![]() 7 8717B–SEEPR–6/10 Atmel AT24C32D/64D Figure 4-2. Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Figure 4-3. Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O Notes: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle SCL SDA IN SDA OUT t F t HIGH t LOW t LOW t R t AA t DH t BUF t SU.STO t SU.DAT t HD.DAT t HD.STA t SU.STA SCL SDA t wr (1) STOP CONDITION START CONDITION WORDn ACK 8th BIT |
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