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TLE6251-2G Datasheet(PDF) 5 Page - Infineon Technologies AG |
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TLE6251-2G Datasheet(HTML) 5 Page - Infineon Technologies AG |
5 / 35 page TLE6251-2G Pin Configuration Data Sheet 5 Rev. 1.0, 2009-05-07 3 Pin Configuration 3.1 Pin Assignment Figure 2 Pin Configuration 3.2 Pin Definitions and Functions 9 Pin Symbol Function 1TxD Transmit Data Input; integrated pull-up resistor to V IO, “Low” for dominant state. 2GND Ground 3 V CC Transceiver Supply Voltage; 100 nF decoupling capacitor to GND recommend. 4RxD Receive Data Output; “Low” in dominant state. Output voltage level dependent on the V IO supply 5 V IO Logic Supply Voltage; Digital Supply Voltage for the logic pins TxD, RxD, EN, NERR and NSTB; Usually connected to the supply voltage of the external microcontroller; 100 nF decoupling capacitor to GND recommend. 6EN Mode Control Input; Integrated pull-down resistor; “High” for Normal operation mode. 7INH Inhibit Output; Open drain output to control external circuitry; High Impedance in Sleep Mode TxD 1 2 3 4 5 6 78 GND VCC RxD NSTB CANH CANL SPLIT VIO EN INH VS WK NERR 9 10 11 12 13 14 |
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