MCM64Z834TQ10R datasheet(25/34 Pages) MOTOROLA

Part #	MCM64Z834TQ10R

Description	256K x 36 and 512K x 18 Bit ZBT Fast Static RAM

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Manufacturer	MOTOROLA [Motorola, Inc]

Direct Link	http://www.freescale.com

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MCM64Z834

•MCM64Z916

25

MOTOROLA FAST SRAM

SERIAL BOUNDARY SCAN TEST ACCESS PORT OPERATION

OVERVIEW

The serial boundary scan test access port (TAP) on this

RAM is designed to operate in a manner consistent with

IEEE Standard 1149.1–1990 (commonly referred to as

JTAG), but does not implement all of the functions required

for IEEE 1149.1 compliance. Certain functions have been

modified or eliminated because their implementation places

extra delays in the RAMs critical speed path. Nevertheless,

the RAM supports the standard TAP controller architecture

(the TAP controller is the state machine that controls the

TAPs operation) and can be expected to function in a manner

that does not conflict with the operation of devices with IEEE

Standard 1149.1 compliant TAPs. The TAP operates using a

2.5 V tolerant logic level signaling.

DISABLING THE TEST ACCESS PORT

It is possible to use this device without utilizing the TAP. To

disable the TAP controller without interfering with normal

operation of the device, TRST should be tied low and TCK,

TDI, and TMS should be pulled through a resistor to 2.5 V.

TDO should be left unconnected.

TAP DC OPERATING CHARACTERISTICS

(TA = 0° to 70°C, Unless Otherwise Noted)

Parameter

Symbol

Min

Max

Unit

Notes

Input Logic Low

VIL1

–0.5

0.7

V

Input Logic High

VIH1

1.7

3

V

Input Leakage Current

Ilkg

—

±10

µA

1

Output Logic Low

VOL1

—

0.7

V

2

Output Logic High

VOH1

1.7

—

V

NOTES:

1. 0 V

≤ Vin ≤ VDDQ for all logic input pins.

2. For VOL = 0.4 V, 14 mA ≤ IOL ≤ 28 mA.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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MCM64Z834TQ10R Datasheet(PDF) 25 Page - Motorola, Inc

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