MCM64Z834

•MCM64Z916

17

MOTOROLA FAST SRAM

Parameter

Symbol

Min

Typ

Max

Unit

Input Capacitance

Cin

—

2

4

pF

Input/Output Capacitance

CI/O

—

3

5

pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(VDD = 2.5 V ±200 mV, TA = 0° to 70°C Unless Otherwise Noted)

Input Timing Measurement Reference Level

1.25 V

. . . . . . . . . . . . . .

Input Pulse Levels

0 to 2.5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time

1.0 V/ns (20% to 80%)

. . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level

1.25 V

. . . . . . . . . . . . . . . . . . . . . . . . .

Output Load

See Figure 9 Unless Otherwise Noted

. . . . . . . . . . . . . .

MCM64Z834–10

MCM64Z916–10

MCM64Z834–11

MCM64Z916–11

MCM64Z834–15

MCM64Z916–15

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Cycle Time

tKHKH

12

—

15

—

20

—

ns

Clock High Pulse Width

tKHKL

4.8

—

6

—

8

—

ns

3

Clock Low Pulse Width

tKLKH

4.8

—

6

—

8

—

ns

3

Clock Access Time

tKHQV

—

10

—

11

—

15

ns

Output Enable to Output Valid

tGLQV

—

5

—

6

—

7

ns

Clock High to Output Active

tKHQX1

1.5

—

1.5

—

1.5

—

ns

4, 5

Output Hold Time

tKHQX

1.5

—

1.5

—

1.5

—

ns

4

Output Enable to Output Active

tGLQX

0

—

0

—

0

—

ns

4, 5

Output Disable to Q High–Z

tGHQZ

—

4.5

—

4.5

—

5

ns

4, 5

Clock High to Q High–Z

tKHQZ

1.5

4.5

1.5

4.5

1.5

5

ns

4, 5

Setup Times:

Address

ADV

Data In

Write

Chip Enable

Clock Enable

tADKH

tLVKH

tDVKH

tWVKH

tEVKH

tCVKH

2.5

2.5

2

2.5

2.5

2.5

—

2.5

2.5

2

2.5

2.5

2.5

—

2.5

2.5

2

2.5

2.5

2.5

—

ns

Hold Times:

Address

ADV

Data In

Write

Chip Enable

Clock Enable

tKHAX

tKHLX

tKHDX

tKHWX

tKHEX

tKHCX

0.5

—

0.5

—

0.5

—

ns

NOTES:

1. Write is defined as any SBx and SW low. Chip enable is defined as SE1 low, SE2 high, and SE3 low whenever ADV is low.

2. All read and write cycle timings are referenced from CK or G.

3. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between

data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some

design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is

given in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.

4. This parameter is sampled and not 100% tested.

5. Measured at

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com