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MCM64Z834TQ10R Datasheet(PDF) 8 Page - Motorola, Inc |
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MCM64Z834TQ10R Datasheet(HTML) 8 Page - Motorola, Inc |
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8 / 34 page  MCM64Z834 •MCM64Z916 8 MOTOROLA FAST SRAM MCM64Z916 PBGA PIN DESCRIPTIONS Pin Locations Symbol Type Description 4B ADV Input Synchronous Load/Advance: Loads a new address into counter when low. RAM uses internally generated burst addresses when high. 4K CK Input Clock: This signal registers the address, data in, and all control signals except G and LBO. 4M CKE Input Clock Enable: Disables the CK input when CKE is high. (a) 6D, 7E, 6F, 7G, 6H, 7K, 6L, 6N, 7P (b) 1D, 2E, 2G, 1H, 2K, 1L, 2M, 1N, 2P DQx I/O Synchronous Data I/O: “x” refers to the byte being read or written (byte a, b). 5J, 5R FT Input Flow–Through Option Input: This pin must remain in steady state (this signal is not registered or latched). It must be tied high or low. Low — flow–through functionality. High — pipelined functionality. 4F G Input Asynchronous Output Enable. 3R LBO Input Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low — linear burst counter. High — interleaved burst counter. 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 2T, 3T, 5T, 6T SA Input Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. 4N, 4P SA1, SA0 Input Synchronous Address Inputs: These pins must be wired to the two LSBs of the address bus for proper burst operation. These inputs are registered and must meet setup and hold times. 5L, 3G (a) (b) SBx Input Synchronous Byte Write Inputs: Enables write to byte “x” (byte a, b) in conjunction with SW. Has no effect on read cycles. 4E SE1 Input Synchronous Chip Enable: Active low to enable chip. 2B SE2 Input Synchronous Chip Enable: Active high for depth expansion. 6B SE3 Input Synchronous Chip Enable: Active low for depth expansion. 4H SW Input Synchronous Write: This signal writes only those bytes that have been selected using the byte write SBx pins. 4U TCK Input Boundary Scan Pin, Test Clock: If boundary scan is not used, TCK must be tied to VDD or VSS. 3U TDI Input Boundary Scan Pin, Test Data In. 5U TDO Output Boundary Scan Pin, Test Data Out. 2U TMS Input Boundary Scan Pin, Test Mode Select. 6U TRST Input Boundary Scan Pin, Asynchronous Test Reset. If boundary scan is not used, TRST must be tied to VSS. 4C, 2J, 3J, 4J, 6J, 1R, 4R VDD Supply Core Power Supply. 1A, 7A, 1F, 7F, 1J, 7J, 1M, 7M, 1U, 7U VDDQ Supply I/O Power Supply. 3D, 5D, 3E, 5E, 3F, 5F, 5G, 3H, 5H, 3K, 5K, 3L, 3M, 5M, 3N, 5N, 3P, 5P, 7T VSS Supply Ground. 4A, 1B, 7B, 1C, 7C, 2D, 4D, 7D, 1E, 6E, 2F, 1G, 6G, 2H, 7H, 1K, 6K, 2L, 4L, 7L, 6M, 2N, 7N, 1P, 6P, 7R, 1T, 4T NC — No Connection: There is no connection to the chip. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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