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MCM64Z834TQ10R Datasheet(PDF) 31 Page - Motorola, Inc |
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MCM64Z834TQ10R Datasheet(HTML) 31 Page - Motorola, Inc |
31 / 34 page ![]() MCM64Z834 •MCM64Z916 31 MOTOROLA FAST SRAM STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES Instruction Code* Description IDCODE 001** Preloads ID register and places it between TDI and TDO. Does not affect RAM operation. HIGH–Z 010 Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins to High–Z. NOT IEEE 1149.1 COMPLIANT. BYPASS 011 Places bypass register between TDI and TDO. Does not affect RAM operation. NOT IEEE 1149.1 COMPLIANT. SAMPLE/PRELOAD 100 Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect RAM operation. Does not implement IEEE 1149.1 Preload function. NOT IEEE 1149.1 COMPLIANT. * Instruction codes expressed in binary, MSB on left, LSB on right. ** Default instruction automatically loaded when TRST asserted or in test–logic–reset state. STANDARD (PRIVATE) INSTRUCTION CODES Instruction Code* Description NO OP 000 Do not use these instructions; they are reserved for future use. NO OP 101 Do not use these instructions; they are reserved for future use. NO OP 110 Do not use these instructions; they are reserved for future use. NO OP 111 Do not use these instructions; they are reserved for future use. * Instruction codes expressed in binary, MSB on left, LSB on right. CAPTURE–DR EXIT1–DR EXIT2–DR UPDATE–DR CAPTURE–IR EXIT1–IR EXIT2–IR UPDATE–IR SHIFT–IR PAUSE–IR PAUSE–DR TEST–LOGIC RESET RUN–TEST/ IDLE SELECT DR–SCAN SELECT IR–SCAN 1 0 1 1 1 1 1 1 1 11 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK. 0 Figure 13. TAP Controller State Diagram 0 SHIFT–DR Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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