 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MCM64Z834TQ10R Datasheet(PDF) 29 Page - Motorola, Inc |
|
|
|||||||||||||||||||||||||||||
MCM64Z834TQ10R Datasheet(HTML) 29 Page - Motorola, Inc |
|
|
29 / 34 page  MCM64Z834 •MCM64Z916 29 MOTOROLA FAST SRAM TEST ACCESS PORT PINS TCK — TEST CLOCK (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS — TEST MODE SELECT (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will not produce the same result as a logic 1 input level (not IEEE 1149.1 compliant). TDI — TEST DATA IN (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is deter- mined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 13). An undriven TDI pin will not pro- duce the same result as a logic 1 input level (not IEEE 1149.1 compliant). TDO — TEST DATA OUT (OUTPUT) Output that is active depending on the state of the TAP state machine (refer to Figure 13). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TRST — TAP RESET The TRST is an asynchronous input that resets the TAP controller and preloads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. TEST ACCESS PORT REGISTERS OVERVIEW The various TAP registers are selected (one at a time) via the sequences of 1s and 0s input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift regis- ters that capture serial input data on the rising edge of TCK and push serial data out on the subsequent falling edge of TCK. When a register is selected, it is “placed” between the TDI and TDO pins. INSTRUCTION REGISTER The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are 3 bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction when TRST is asserted or whenever the controller is placed in the test–logic–reset state. The two least significant bits of the serial instruction register are loaded with a binary “or” pattern in the capture–IR state. BYPASS REGISTER The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. BOUNDARY SCAN REGISTER The boundary scan register is identical in length to the number of active input and I/O connections on the RAM (not counting the TAP pins). This also includes a number of place holder locations (always set to a logic 0) reserved for density upgrade address pins. There are a total of 67 bits in the case of the x36 device and 48 bits in the case of the x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture–DR state and then is placed between the TDI and TDO pins when the controller is moved to shift–DR state. The Bump/Bit Scan Order table describes which device bump connects to each boundary scan register location. The first column defines the bit’s position in the boundary scan register. The shift register bit nearest TDO (i.e., first to be shifted out) is defined as bit 1. The second column is the name of the input or I/O at the bump and the third column is the bump number. IDENTIFICATION (ID) REGISTER The ID register is a 32–bit register that is loaded with a de- vice and vendor specific 32–bit code when the controller is put in capture–DR state with the IDCODE command loaded in the instruction register. The code is loaded from a 32–bit on–chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into shift–DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Presence Indicator Bit No. 0 Value 1 Motorola JEDEC ID Code (Compressed Format, per IEEE Standard 1149.1–1990 Bit No. 11 10 9 8 7 6 5 4 3 2 1 Value 0 0 0 0 0 0 0 1 1 1 0 Reserved For Future Use Bit No. 17 16 15 14 13 12 Value x x x x x x Device Width Bit No. 22 21 20 19 18 256K x 36 0 0 1 0 0 512K x 18 0 0 0 1 1 Device Depth Bit No. 27 26 25 24 23 256K x 36 0 0 1 1 0 512K x 18 0 0 1 1 1 Revision Number Bit No. 31 30 29 28 Value 0 0 0 0 Figure 12. ID Register Bit Meanings Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
Similar Part No. - MCM64Z834TQ10R |
|
Similar Description - MCM64Z834TQ10R |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
