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313079-001 Datasheet(PDF) 17 Page - Intel Corporation |
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313079-001 Datasheet(HTML) 17 Page - Intel Corporation |
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17 / 104 page  Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 17 Electrical Specifications The processor core frequency is configured during reset by using values stored internally during manufacturing. The stored value sets the highest bus fraction at which the particular processor can operate. If lower speeds are desired, the appropriate ratio can be configured via the IA32_FLEX_BRVID_SEL MSR. For details of operation at core frequencies lower than the maximum rated processor speed, refer to the IA-32 Intel® Architecture Software Developer’s Manual, Volume 3A &3B. Clock multiplying within the processor is provided by the internal phase locked loop (PLL), which requires a constant frequency BCLK[1:0] input, with exceptions for spread spectrum clocking. The Dual-Core Intel Xeon Processor 5000 series utilize differential clocks. Table 2-1 contains processor core frequency to FSB multipliers and their corresponding core frequencies. Notes: 1. Individual processors operate only at or below the frequency marked on the package. 2. Listed frequencies are not necessarily committed production frequencies. 3. For valid processor core frequencies, refer to the Dual-Core Intel® Xeon® Processor 5000 series Specification Update. 4. Mid-voltage (MV) processors only. 5. The lowest bus ratio supported by the Dual-Core Intel Xeon Processor 5000 series is 1/12. 2.4.1 Front Side Bus Frequency Select Signals (BSEL[2:0]) Upon power up, the FSB frequency is set to the maximum supported by the individual processor. BSEL[2:0] are open drain outputs which must be pulled up to VTT, and are used to select the FSB frequency. Please refer to Table 2-12 for DC specifications. Table 2-2 defines the possible combinations of the signals and the frequency associated with each combination. The frequency is determined by the processor(s), chipset, and clock synthesizer. All FSB agents must operate at the same core and FSB frequency. See the appropriate platform design guidelines for further details. Table 2-1. Core Frequency to FSB Multiplier Configuration Core Frequency to FSB Multiplier Core Frequency with 166 MHz FSB Clock Processor Number Notes 1/16 2.67 GHz 5030 1, 2, 3, 4 1/18 3 GHz 5050 1, 2, 3, 4 Core Frequency to FSB Multiplier Core Frequency with 266 MHz FSB Clock Notes 1/12 3.20 GHz 5063 1, 2, 3, 4 1/12 3.20 GHz 5060 1, 2, 3, 5 1/14 3.73 GHz 5080 1, 2, 3 Table 2-2. BSEL[2:0] Frequency Table BSEL2 BSEL1 BSEL0 Bus Clock Frequency 0 0 0 266.67 MHz 001 Reserved 010 Reserved 0 1 1 166.67 MHz 100 Reserved 101 Reserved 110 Reserved 111 Reserved |
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