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313079-001 Datasheet(PDF) 15 Page - Intel Corporation |
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313079-001 Datasheet(HTML) 15 Page - Intel Corporation |
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15 / 104 page  Dual-Core Intel® Xeon® Processor 5000 Series Datasheet 15 Electrical Specifications 2 Electrical Specifications 2.1 Front Side Bus and GTLREF Most Dual-Core Intel Xeon Processor 5000 series FSB signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up resistors to provide the high logic level and termination. AGTL+ output buffers differ from GTL+ buffers with the addition of an active PMOS pull-up transistor to “assist” the pull-up resistors during the first clock of a low-to-high voltage transition. Platforms implement a termination voltage level for AGTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address buses have made signal integrity considerations and platform design methods even more critical than with previous processor families. The AGTL+ inputs require reference voltages (GTLREF), which are used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the baseboard. GTLREF is a generic name for GTLREF_DATA_C[1:0], the reference voltages for the 4X data bus and GTLREF_ADD_C[1:0], the reference voltages for the 2X address bus and common clock signals. Refer to the applicable platform design guidelines for details. Termination resistors (RTT) for AGTL+ signals are provided on the processor silicon and are terminated to VTT. The on-die termination resistors are always enabled on the Dual-Core Intel Xeon Processor 5000 series to control reflections on the transmission line. Intel chipsets also provide on-die termination, thus eliminating the need to terminate the bus on the baseboard for most AGTL+ signals. Some FSB signals do not include on-die termination (RTT) and must be terminated on the baseboard. See Table 2-7 for details regarding these signals. The AGTL+ bus depends on incident wave switching. Therefore, timing calculations for AGTL+ signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the FSB, including trace lengths, is highly recommended when designing a system. Contact your Intel Field Representative to obtain the processor signal integrity models, which includes buffer and package models. 2.2 Power and Ground Lands For clean on-chip processor core power distribution, the processor has 223 VCC (power) and 271 VSS (ground) inputs. All Vcc lands must be connected to the processor power plane, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. See Table 2-3 for VID definitions. Twenty two lands are specified as VTT, which provide termination for the FSB and power to the I/O buffers. The platform must implement a separate supply for these lands which meets the VTT specifications outlined in Table 2-10. |
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