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MB90800 Datasheet(PDF) 26 Page - Fujitsu Component Limited. |
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MB90800 Datasheet(HTML) 26 Page - Fujitsu Component Limited. |
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26 / 92 page  MB90800 Series 26 DS07-13733-6E (2) Port direction register When each terminal functions as a port, each correspondent pin are controlled by the port direction register to following; 0 : Input mode 1 : Output mode This bit becomes “0” after a reset. Note : When accessing this register by using the instruction of the read modify write system (instructions such as bit set) is mode, the bit targeted by an instruction becomes the defined value. However, the content of the output register set to input with the other changes to input value of the pin at that time. Therefore, be sure to write an expected value into PDR firstly, and then set DDR and finally change to the output when changing the input pin to the output pin is made. - : Unused DDR0 bit Initial Value Access Address : 000010H 00000000B R/W DDR1 bit Address : 000011H 00000000B R/W DDR2 bit Address : 000012H 00000000B R/W DDR3 bit Address : 000013H 00000000B R/W DDR4 bit Address : 000014H 00000000B R/W DDR5 bit Address : 000015H 00000000B R/W DDR6 bit Address : 000016H 00000000B R/W DDR7 bit Address : 000017H - 0000000B R/W DDR8 bit Address : 000018H - - - 00000B R/W DDR9 bit Address : 000019H - - - - - - 00B R/W 76 5 4 3 21 0 D06 D07 D05 D04 D03 D02 D01 D00 15 14 13 12 11 10 9 8 D16 D17 D15 D14 D13 D12 D11 D10 76 5 4 3 2 1 0 D26 D27 D25 D24 D23 D22 D21 D20 15 14 13 12 11 10 9 8 D36 D37 D35 D34 D33 D32 D31 D30 76 5 4 3 2 1 0 D46 D47 D45 D44 D43 D42 D41 D40 15 14 13 12 11 10 9 8 D56 D57 D55 D54 D53 D52 D51 D50 76 5 4 3 2 1 0 D66 D67 D65 D64 D63 D62 D61 D60 15 14 13 12 11 10 9 8 D75 D74 D73 D72 D71 D70 D76 ⎯ 76 5 4 3 2 1 0 D84 D83 D82 D81 D80 ⎯ ⎯ ⎯ 15 14 13 12 11 10 9 8 D91 D90 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ |
Similar Part No. - MB90800_09 |
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Similar Description - MB90800_09 |
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