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MB90800 Datasheet(PDF) 61 Page - Fujitsu Component Limited. |
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MB90800 Datasheet(HTML) 61 Page - Fujitsu Component Limited. |
61 / 92 page ![]() MB90800 Series DS07-13733-6E 61 16. Timer clock output The timer clock output circuit divides the oscillation clock by the time-base timer and generates and outputs the set division clock. Selectable from 32/64/128/256 division of the oscillation clock. The timer clock output circuit is inactive in reset or stop mode. It is active in normal run, sleep, or pseudo-timer mode. Note : When the time-base timer is cleared while using the timer clock output circuit, the clock is not correctly output. For detail of the time-base timer’s clear condition, see the section of time-base timer in the MB90800 Hardware Manual. (1) Register list (2) Block diagram PLL_Run Main_Run Sleep Pseudo clock STOP Reset Operation status × × Watch clock output control register (TMCS) - : Unused bit Initial Value 0000AFH XXXXX000B Read/Write R/W R/W R/W 15 14 13 12 11 10 9 8 ⎯ ⎯⎯ ⎯ ⎯ TEN TS1 TS0 ⎯ ⎯⎯ ⎯ ⎯ X0 X1 Timer clock selection circuit Oscillation circuit Timer clock output Selector Time-base timer Dividing by 2 |
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Similar Description - MB90800_09 |
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