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MB90800 Datasheet(PDF) 59 Page - Fujitsu Component Limited. |
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MB90800 Datasheet(HTML) 59 Page - Fujitsu Component Limited. |
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59 / 92 page  MB90800 Series DS07-13733-6E 59 (2) Block diagram SCM HCLK SCLK MCM WS1 WS0 SCS MCS CS1 CS0 STP SLP SPL RST TMD CG1 CG0 2 2 X0A X1A RST X0 X1 MCLK Reserved Low power consumption mode control register (LPMCR) Release of interrupt CPU intermittent operation selector Pin High-Z control circuit Clock selector Sub clock generation circuit Pin Oscillation stabilization wait time selector Clock selection register (CKSCR) Time-base timer Pin Peripheral clock control Internal reset generation circuit Standby control circuit PLL multiplying circuit Pin Pin To watchdog timer Dividing by 1024 HCLK : Oscillation clock MCLK : Main clock SCLK : Sub clock Standby control circuit CPU clock control circuit Pin System clock generation circuit Dividing by 2 Dividing by 2 Dividing by 4 Dividing by 4 Dividing by 4 Dividing by 2 Clock generation block Machine clock Release of oscillation stabilization wait Pin High-Z control CPU clock Internal reset Stop, sleep signal Stop signal Peripheral clock Intermittent cycle selection Dividing by 4 |
Similar Part No. - MB90800_09 |
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Similar Description - MB90800_09 |
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