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MB90800 Datasheet(PDF) 50 Page - Fujitsu Component Limited. |
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MB90800 Datasheet(HTML) 50 Page - Fujitsu Component Limited. |
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50 / 92 page  MB90800 Series 50 DS07-13733-6E 10. 16-bit reload timer The 16-bit reload timer provides two functions either one which can be selected, the internal clock mode that performs the count down by synchronizing with 3-type internal clocks and the event count mode that performs the count down by detecting the arbitration. This timer defines an underflow as a transition of the count value from 0000H to FFFFH. Therefore, when the equation (counted value = reload register setting value+1) holds, an underflow occurs. Either mode can be selected for the count operation from the reload mode which repeats the count by reloading the count setting value at the underflow occurrence or the one-shot mode which stops the count at the underflow occurrence. The interrupt can be generated at the counter underflow occurrence so as to correspond to the DTC. (1) Register list • TMCSR Timer control status register Timer control status register (upper) (TMCSR0H to TMCSR2H) Timer control status register (lower) (TMCSR0L to TMCSR2L) • 16-bit timer register/16-bit reload register TMR0 to TMR2/TMRLR0 to TMRLR2 (upper) TMR0 to TMR2/TMRLR0 to TMRLR2 (lower) - : Unused bit Initial Value 000051H 000055H 000059H - - - - 0000B Read/Write bit Initial Value 000050H 000054H 000058H 00000000B Read/Write bit Initial Value 000053H 000057H 00005BH XXXXXXXXB Read/Write bit Initial Value 000052H 000056H 00005AH XXXXXXXXB Read/Write ⎯⎯ ⎯ R/W R/W R/W R/W 15 14 13 12 11 10 9 8 ⎯ ⎯ ⎯⎯ ⎯ CSL1 CSL0 MOD2 MOD1 R/W R/W R/W R/W R/W R/W R/W 76 5 4 3 2 1 0 OUTE R/W MOD0 OUTL RELD INTE UF CNTE TRG R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 D14 R/W D15 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W 76 5 4 3 2 1 0 D6 R/W D7 D5 D4 D3 D2 D1 D0 |
Similar Part No. - MB90800_09 |
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Similar Description - MB90800_09 |
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