5

FN6738.1

January 7, 2009

SWITCHING REGULATOR

Frequency

330

400

440

kHz

BOOT Supply Current

UGATE High

170

290

400

µA

PHASE Input Bias Current

0

2

µA

UGATE ON-Resistance Low

0.9

1.6

Ω

UGATE ON-Resistance High

1.4

2.5

Ω

LGATE ON-Resistance High

1.4

2.5

Ω

LGATE ON-Resistance Low

0.9

1.6

Ω

Dead Time

Falling UGATE to rising LGATE or

falling LGATE to rising UGATE

35

50

80

ns

ERROR AMPLIFIERS

GMV Amplifier Transconductance

200

250

300

µA/V

GMI Amplifier Transconductance

40

50

60

µA/V

GMS Amplifier Transconductance

40

50

60

µA/V

GMI/GMS Saturation Current

15

21

25

µA

GMV Saturation Current

10

17

30

µA

ICOMP, VCOMP Clamp Voltage

200

300

400

mV

LOGIC LEVELS

SDA/SCL Input Low Voltage

VDDSMB = 2.7V to 5.5V

0.8

V

SDA/SCL Input High Voltage

VDDSMB = 2.7V to 5.5V

2

V

SDA/SCL Input Bias Current

VDDSMB = 2.7V to 5.5V

-1

1

µA

SDA, Output Sink Current

7

15

mA

Electrical Specifications

DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V,

at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production

tested. (Continued)

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

PARAMETERS

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

SMBus Frequency

FSMB

10

100

kHz

Bus Free Time

TBUF

4.7

µs

Start Condition Hold Time from SCL

THD:STA

4

µs

Start Condition Setup Time from SCL

TSU:STA

4.7

µs

Stop Condition Setup Time from SCL

TSU:STO

4

µs

SDA Hold Time from SCL

THD:DAT

300

ns

SDA Setup Time from SCL

TSU:DAT

250

ns

SCL Low Timeout (Note 3)

TTIMEOUT

22

25

30

ms

SCL Low Period

TLOW

4.7

µs

SCL High Period

THIGH

4

µs

Maximum Charging Period Without a SMBus Write to

ChargeVoltage or ChargeCurrent Register

140

180

220

s

NOTES:

3. If SCL is low for longer than the specified time, the charger is disabled.

4. Limits established by characterization and are not production tested.

ISL88731A