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ATMEGA8515 Datasheet(PDF) 41 Page - ATMEL Corporation |
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ATMEGA8515 Datasheet(HTML) 41 Page - ATMEL Corporation |
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41 / 257 page  41 ATmega8515(L) 2512K–AVR–01/10 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a SLEEP instruction must be executed. The SM2 bit in MCUCSR, the SM1 bit in MCUCR, and the SM0 bit in the EMCUCR Register select which sleep mode (Idle, Power-down, or Standby) will be activated by the SLEEP instruction. See Table 16 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, it exe- cutes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a Reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 18 on page 34 presents the different clock systems in the ATmega8515, and their distribution. The figure is helpful in selecting an appropriate sleep mode. MCU Control Register – MCUCR • Bit 5 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after wak- ing up. • Bit 4 – SM1: Sleep Mode Select Bit 1 The Sleep Mode Select bits select between the three available sleep modes as shown in Table 16. MCU Control and Status Register – MCUCSR • Bit 5 – SM2: Sleep Mode Select Bit 2 The Sleep Mode Select bits select between the three available sleep modes as shown in Table 16. Bit 7654 321 0 SRE SRW10 SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 Bit 7654 321 0 – –SM2 – WDRF BORF EXTRF PORF MCUCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0000 000 0 |
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