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ATMEGA8515 Datasheet(PDF) 81 Page - ATMEL Corporation |
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ATMEGA8515 Datasheet(HTML) 81 Page - ATMEL Corporation |
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81 / 257 page  81 ATmega8515(L) 2512K–AVR–01/10 inactive when no clock source is selected. The output from the clock select logic is referred to as the timer clock (clk T0). The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Wave- form Generator to generate a PWM or variable frequency output on the Output Compare Pin (OC0). See “Output Compare Unit” on page 82. for details. The Compare Match event will also set the Compare Flag (OCF0) which can be used to generate an output compare interrupt request. Definitions Many register and bit references in this document are written in general form. A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 43 are also used extensively throughout the document. Timer/Counter Clock Sources The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the clock select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 95. Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 35 shows a block diagram of the counter and its surroundings. Figure 35. Counter Unit Block Diagram Signal description (internal signals): count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). Table 43. Definitions BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The assignment is dependent on the mode of operation. DATA BUS TCNTn Control Logic count TOVn (Int.Req.) Clock Select top Tn Edge Detector ( From Prescaler ) clk Tn bottom direction clear |
Similar Part No. - ATMEGA8515_10 |
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Similar Description - ATMEGA8515_10 |
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